Methods and Systems for Inspection of Wafers and Reticles Using Designer Intent Data

Abstract

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

1 . A system, comprising a computer processor configured for identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, wherein the reticle is used to form a pattern on the wafer prior to inspection of the wafer. 
     
     
         2 . The system of  claim 1 , wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects. 
     
     
         3 . The system of  claim 1 , wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects based on designer intent data. 
     
     
         4 . The system of  claim 1 , wherein the computer processor is further configured for separating the nuisance defects from actual defects on the wafer and processing data representative of the actual defects. 
     
     
         5 . The system of  claim 1 , further comprising an additional computer processor configured for transmitting the inspection data from an inspection system used to perform the inspection of the reticle to the computer processor. 
     
     
         6 . The system of  claim 1 , further comprising an additional computer processor configured for transmitting the inspection data from a fab database to the computer processor. 
     
     
         7 . The system of  claim 6 , wherein said transmitting comprises sending coordinates of defects detected on the reticle and images of the defects. 
     
     
         8 . The system of  claim 1 , wherein the inspection data comprises coordinates of a location of a defect on the reticle, and wherein the computer processor is further configured for translating the coordinates to coordinates of locations of one or more of the nuisance defects on the wafer. 
     
     
         9 . The system of  claim 1 , wherein the computer processor is further configured for determining if the nuisance defects will affect yield of semiconductor devices, and wherein the semiconductor devices will be formed on the wafer. 
     
     
         10 . The system of  claim 1 , wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects, and wherein the computer processor is further configured for analyzing the nuisance defects to determine if the permissible reticle defects were correctly classified. 
     
     
         11 . The system of  claim 10 , wherein if the permissible reticle defects were not correctly classified, the computer processor is further configured for determining if the reticle should be analyzed, reworked, or disposed. 
     
     
         12 . The system of  claim 1 , wherein the computer processor is further configured for generating a two-dimensional map of the wafer, and wherein the nuisance defects are distinguished from other defects in the map by one or more different designations. 
     
     
         13 . A system, comprising a computer processor configured for identifying locations on a wafer in which nuisance defects will be formed based on inspection data produced by inspection of a reticle. 
     
     
         14 . The system of  claim 13 , wherein the computer processor is further configured for selecting one or more parameters for wafer inspection such that the locations are not inspected. 
     
     
         15 . The system of  claim 13 , wherein the computer processor is further configured for selecting one or more parameters for wafer defect review such that the nuisance defects are not reviewed. 
     
     
         16 . The system of  claim 13 , wherein the computer processor is further configured for selecting one or more parameters for wafer defect analysis such that the nuisance defects are not analyzed. 
     
     
         17 . A system, comprising a computer processor configured for:
 identifying critical portions of a wafer based on criticality associated with different areas of the wafer; and   selecting parameters for inspection of the wafer such that only the critical portions of the wafer are inspected.   
     
     
         18 . The system of  claim 17 , wherein the parameters are selected such that the critical portions having different criticalities inspected with different parameters. 
     
     
         19 . The system of  claim 17 , wherein the computer processor is further configured for translating coordinates of a location of a defect detected on a reticle to coordinates of locations of one or more defects on the wafer and analyzing the printability of the defect detected on the reticle. 
     
     
         20 . The system of  claim 17 , wherein the computer processor is further configured for translating coordinates of a location of a defect detected on a reticle to coordinates of locations of one or more defects on the wafer and removing inspection data at the coordinates on the wafer from wafer inspection data. 
     
     
         21 . The system of  claim 17 , wherein the computer processor is further configured for generating one or more two-dimensional maps illustrating the critical portions of the wafer. 
     
     
         22 . The system of  claim 17 , wherein said selecting comprises selecting the parameters such that nuisance defects on the wafer are not classified as actual defects. 
     
     
         23 . The system of  claim 17 , wherein the computer processor is further configured for assigning a designation to a defect on the wafer based on the criticality of the critical portion in which the defect is located. 
     
     
         24 . The system of  claim 17 , wherein the computer processor is further configured for determining processing of a defect on the wafer based on the criticality of the critical portion in which the defect is located. 
     
     
         25 . The system of  claim 17 , wherein the computer processor is further configured for setting one or more parameters for classification of defects on the wafer based on the criticality of the critical portions. 
     
     
         26 . The system of  claim 17 , wherein the computer processor is further configured for classifying defects on the wafer as critical defects or non-critical defects and analyzing a process performed on the wafer based on the critical defects and the non-critical defects. 
     
     
         27 . The system of  claim 17 , wherein the computer processor is further configured for classifying defects on the wafer as critical defects or non-critical defects and processing the critical defects separately from the non-critical defects. 
     
     
         28 . The system of  claim 17 , wherein the computer processor is further configured for discarding inspection data representing defects in one of the critical portions if the defects have a lateral dimension smaller than a predetermined threshold and if other features in the one portion have a lateral dimension greater than the predetermined threshold. 
     
     
         29 . The system of  claim 17 , wherein the computer processor is further configured for discarding inspection data representing defects in one of the critical portions if an element of a circuit in the one portion has a predetermined amount of redundancy and if defects in the one portion do not exceed a predetermined density threshold. 
     
     
         30 . The system of  claim 17 , wherein the inspection is performed on one level of the wafer, and wherein the computer processor is further configured for identifying the criticality of a defect on the wafer based on the criticality of the critical portion in which the detect is located and data representative of at least one layer of the wafer above or below the one level. 
     
     
         31 . The system of  claim 30 , wherein the computer processor is further configured for generating a three-dimensional representation of the defect, the one level, and the at least one layer of the wafer. 
     
     
         32 . A system, comprising a computer processor configured for determining one or more parameters for wafer defect review based on criticality associated with different areas of the wafer. 
     
     
         33 . The system of  claim 32 , wherein the computer processor is further configured for selecting the one or more parameters such that only defects located in critical portions of the wafer are reviewed. 
     
     
         34 . The system of  claim 33 , wherein the one or more parameters are different for one or more of the critical portions. 
     
     
         35 . The system of  claim 32 , wherein the computer processor is further configured for sending information about the criticality to a tool configured to perform the wafer defect review. 
     
     
         36 . A system, comprising a computer processor configured for determining one or more parameters fur wafer defect analysis based on criticality associated with different areas of the wafer. 
     
     
         37 . The system of  claim 36 , wherein the computer processor is further configured for selecting the one or more parameters such that only defects located in critical portions of the wafer are analyzed. 
     
     
         38 . The system of  claim 37 , wherein the one or more parameters are different for one or more of the critical portions. 
     
     
         39 . The system of  claim 36 , wherein the computer processor is further configured for sending information about the criticality to a tool configured to perform the wafer defect analysis. 
     
     
         40 .- 85 . (canceled)