US2016141169A1PendingUtilityA1

Substrate backside texturing

Assignee: TOKYO ELECTRON LTDPriority: Aug 9, 2013Filed: Jan 26, 2016Published: May 19, 2016
Est. expiryAug 9, 2033(~7 yrs left)· nominal 20-yr term from priority
H10P 74/203H10P 74/23H10P 72/76H10P 52/402H10P 90/124H01L 22/20H01L 21/687H01L 21/02016G03F 7/70783H10P 52/00
47
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Claims

exact text as granted — not AI-modified
1 . A method, comprising:
 determining one or more contact areas on a photolithography tool for the semiconductor substrate;   determining a backside surface friction for a semiconductor substrate that is based, at least in part, on:
 a frequency of backside features of the semiconductor substrate at one or more portions of the semiconductor substrate, or 
 an amplitude of the backside features at the one or more portions of the semiconductor substrate; and 
   processing the semiconductor substrate to obtain a target backside surface friction on the semiconductor substrate, the target backside surface friction comprising backside surface features at a period that is no more than ⅕ of a size of the one or more contact areas.   
     
     
         2 . The method of  claim 1 , wherein the contact areas comprise a density of no more than 70 per millimeter. 
     
     
         3 . The method of  claim 2 , wherein the amplitude of the backside features varies by no more than 10 nm of each other. 
     
     
         4 . The method of  claim 1 , wherein the processing comprises:
 applying one or more films to the backside of the semiconductor substrate with at least one chemical agent.   
     
     
         5 . The method of  claim 1 , wherein the processing comprises applying a film to the backside of the semiconductor substrate using a vapor deposition process. 
     
     
         6 . The method of  claim 5 , wherein the vapor deposition process comprises HMDS. 
     
     
         7 . The method of  claim 6 , wherein the processing further comprises changing a surface energy of the semiconductor substrate. 
     
     
         8 . The method of  claim 6 , wherein the processing further comprises changing material characteristics or properties of the semiconductor substrate at an atomic level. 
     
     
         9 . A method for improving backside surface friction of a semiconductor substrate, comprising:
 determining a type of photolithography tool that will be used to process the semiconductor substrate, the photolithography tool comprising one or more contact areas that will support the semiconductor substrate ; and   processing the semiconductor substrate to obtain a backside surface friction that is based, at least in part, on backside features occurring at a period no more than ⅕ of a size of the contact areas.   
     
     
         10 . The method of  claim 9 , wherein the the backside surface friction is based, at least in part, on distances between features on the backside of the semiconductor substrate. 
     
     
         11 . The method of  claim 9 , wherein the the backside surface friction is based, at least in part, on amplitudes of the features on the backside of the semiconductor substrate. 
     
     
         12 . The method of  claim 9 , wherein the backside surface friction comprises a horizontal distance component that is less than a width of the one or more contact areas for at least a portion of the backside of the semiconductor substrate. 
     
     
         13 . The method of  claim 9 , wherein the backside surface friction further comprises a vertical distance component that is within 50 nm across at least a portion of the backside of the semiconductor substrate. 
     
     
         14 . A method of reducing lithographic distortion comprising:
 treating a backside of a semiconductor substrate; and   performing a lithographic process on the semiconductor substrate having the treated backside with a lithographic tool which supports the semiconductor substrate at one or more contact areas, the treating reduces the coefficient of friction between the backside and the one or more contact areas, and the coefficient of friction based, least in part, on the backside comprising features of a period that is no more than ⅕ of a size of the one or more contact areas.   
     
     
         15 . The method of  claim 14 , wherein the treating of the backside is based, at least in part, on changing a surface energy of the backside of the semiconductor substrate. 
     
     
         16 . The method of  claim 14 , wherein the treating comprises applying a vapor to the backside of the semiconductor substrate. 
     
     
         17 . The method of  claim 14 , wherein the treated backside contacts each of the one or more contact areas at a frequency of 5-10 contacts per micron. 
     
     
         18 . The method of  claim 14 , wherein the features vary in distance in a direction perpendicular to a surface of the semiconductor substrate by no more than 10 nm. 
     
     
         19 . The method of  claim 14 , further comprising:
 producing an image on a front surface of the semiconductor substrate;   measuring variations in the image from a reference; and   producing a modified image on a front surface of a subsequent substrate that varies from the image in accordance with the variations.

Join the waitlist — get patent alerts

Track US2016141169A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.