Semiconductor device with through-mold via

Abstract

In accordance with the present invention, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.

1 . A packaged semiconductor device structure comprising:
 a first redistribution structure comprising:
 a first insulative structure including at least one insulating layer, the first insulative structure having a first major surface and an opposing second major surface; 
 a first conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure, wherein the first conductive pattern comprises a first portion disposed proximate to a perimeter part of the first redistribution structure and a second portion disposed proximate to a central part of the first redistribution structure; and 
 a second conductive pattern disposed proximate to the second major surface of the first insulative structure and electrically coupled to the first conductive pattern, wherein at least a portion of the second conductive pattern is exposed to the outside of the first insulative structure; 
   a first semiconductor device electrically coupled to the second portion of the first conductive pattern with conductive bumps;   first conductive structures projecting outward from and electrically coupled to the first portion of the first conductive pattern;   a package body encapsulating the first semiconductor device, at least portions of the first redistribution structure, and parts of the first conductive structures, wherein portions of the first conductive structures distal to the first redistribution structure are exposed to the outside of the package body, and wherein the portions of the first conductive structures distal to the first redistribution structure reside on a plane that is elevated above at least a portion of the package body; and   a second redistribution structure electrically coupled to the portions of the first conductive structures distal to the first redistribution structure.   
     
     
         2 . The structure of  claim 1 , wherein the first conductive structures comprise conductive vias. 
     
     
         3 . The structure of  claim 1 , wherein the first conductive structures comprise conductive balls. 
     
     
         4 . The structure of  claim 1 , wherein the first conductive structures comprise a combination of conductive balls and conductive vias. 
     
     
         5 . The structure of  claim 1 , wherein the portions of the first conductive structures distal to the first redistribution structure provide a gap between the package body and the second redistribution structure. 
     
     
         6 . The structure of  claim 5 , wherein a major surface of the first semiconductor device is exposed to the outside of the package body in the gap. 
     
     
         7 . The structure of  claim 1 , wherein the second redistribution structure is configured to selectively redistribute a wiring pattern of the first conductive structures. 
     
     
         8 . The structure of  claim 1  further comprising:
 a third conductive pattern disposed within the first insulative structure and electrically coupling the first conductive pattern to the second conductive pattern; and 
 second conductive structures projecting outward from and electrically coupled to the portion of the second conductive layer exposed to the outside of the first insulative structure. 
 
     
     
         9 . The structure of  claim 8  further comprising:
 a substrate comprising a substrate conductive pattern; and 
 a second semiconductor device electrically coupled to a first portion of the substrate conductive pattern, wherein: 
 the second conductive structures are further electrically coupled to a second portion of the substrate conductive pattern; and 
 the package body further encapsulates the second semiconductor device, the second conductive structures, and at least portions of the substrate conductive pattern. 
 
     
     
         10 . The structure of  claim 9  further comprising an adhesive layer interposed between the first redistribution structure and the first semiconductor device. 
     
     
         11 . The structure of  claim 1 , wherein the second redistribution structure comprises:
 a second insulative structure including at least one insulating layer, the second insulative structure having a first major surface and an opposing second major surface;   a third conductive pattern disposed proximate to the first major surface of the second insulative structure and exposed to the outside of the second insulative structure and configured for receiving an electronic component;   a fourth conductive pattern disposed proximate to the second major surface of the second insulative structure, wherein at least a portion of the fourth conductive pattern is exposed to the outside of the second insulative structure, and wherein the fourth conductive pattern is electrically coupled to the first conductive structures; and   a fifth conductive pattern disposed within the second insulative structure and electrically coupling the third conductive pattern to the fourth conductive pattern.   
     
     
         12 . A packaged semiconductor device structure comprising:
 a first redistribution structure comprising:
 a first insulative structure including at least one insulating layer, the first insulative structure having a first major surface and an opposing second major surface; 
 a first conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure; 
 a second conductive pattern disposed proximate to the second major surface of the first insulative structure, wherein at least a portion of the second conductive pattern is exposed to the outside of the first insulative structure; and 
 a third conductive pattern disposed within the first insulative structure and electrically coupling the first conductive pattern to the second conductive pattern; 
   a first semiconductor device electrically coupled to the first conductive pattern;   a substrate comprising a substrate conductive pattern, wherein the second conductive pattern is electrically coupled to the substrate conductive pattern;   first conductive structures projecting outward from and electrically coupled to the substrate conductive pattern and laterally spaced apart from the first semiconductor device; and   a package body encapsulating the first redistribution structure, the first semiconductor device, and the first conductive structures, wherein portions of the first conductive structures distal to the substrate conductive pattern are exposed to the outside of the package body.   
     
     
         13 . The structure of  claim 12 , wherein the first conductive structures each comprise:
 a first region attached to the substrate conductive pattern; and   a second region different than the first region coupled to the first region, wherein the portions of the first conductive structures exposed to the outside of the package body are part of the second region, and wherein:   the portions of the first conductive structures distal to the substrate conductive pattern reside on a plane that is elevated above the first semiconductor device.   
     
     
         14 . The structure of  claim 13 , wherein:
 the first region comprises a conductive ball; and   the second region comprises a conductive via.   
     
     
         15 . The structure of  claim 12  further comprising a second semiconductor device having a plurality of conductive vias disposed extending through the second semiconductor device, wherein the plurality of conductive vias electrically couple the second conductive pattern of the first redistribution structure to the substrate conductive pattern, and wherein the package body completely encapsulates the first redistribution structure. 
     
     
         16 . A packaged semiconductor device structure comprising:
 a first substrate structure having a first major surface and an opposing second major surface, the first substrate structure comprising:
 a first conductive pattern disposed proximate to the first major surface of the first substrate structure; and 
 a second conductive pattern disposed proximate to the second major surface of the first substrate structure and electrically coupled to the first conductive pattern; 
   a first semiconductor device electrically coupled to the first conductive pattern;   a second substrate structure comprising:
 a first insulative structure including at least one insulating layer, the first insulative structure having a first major surface and an opposing second major surface; 
 a third conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure; and 
 a fourth conductive pattern disposed proximate to the second major surface of the first insulative structure and electrically coupled to the third conductive pattern, wherein at least a portion of the fourth conductive pattern is exposed to the outside of the first insulative structure; 
   a second semiconductor device electrically coupled to the third conductive pattern;   an adhesive layer interposed between the first semiconductor device and the second major surface of the second substrate structure;   first conductive structures extending upright from and electrically coupled to the first conductive pattern and electrically coupled to the fourth conductive pattern;   and   a package body encapsulating at least portions of the first semiconductor device and the first conductive structures.   
     
     
         17 . The structure of  claim 16  further comprising:
 second conductive structures extending upright and electrically coupled to the third conductive pattern, wherein:
 at least portions of the second semiconductor device, at least portions of the second substrate structure, and first portions of the second conductive structures are encapsulated by the package body; and 
 second portions of the second conductive structures are exposed to the outside of the package body; and 
 
 a third substrate structure electrically coupled to the second portions of the second conductive. 
 
     
     
         18 . The structure of  claim 17 , wherein:
 distal ends of the second portions of the second conductive structures reside on a plane that is elevated above the package body to provide a gap between the package body and the third substrate structure.   
     
     
         19 . The structure of  claim 16 , wherein the first semiconductor device is electrically coupled to the first conductive pattern with conductive bumps. 
     
     
         20 . The structure of  claim 17 , wherein the second substrate structure is completely encapsulated by the package body.