Interconnect structure for a microelectronic device

Abstract

A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

1 . A method for forming a microelectronic device package, comprising:
 forming a molded structure over a first semiconductor die,
 wherein the die includes first and second groups of contacts, 
 wherein the contacts of each of the first and second groups are respectively arranged at first and second pitches, and 
 wherein the contacts of the second group are at a finer pitch than the contacts of the first group; 
   forming a redistribution layer over the first semiconductor die and at least a portion of the molded structure, wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and a molded component, wherein the molded component extends around the first semiconductor die; and   coupling a second semiconductor die to the first semiconductor die, the second semiconductor die on the opposite side of the redistribution layer from the first semiconductor die,
 wherein the second semiconductor die includes a third group of contacts arranged at the same pitch as the contacts the second group, and 
 wherein the second semiconductor die is coupled to the first semiconductor die at least in part by bonding contacts of the third group to respective contacts of the second group, and 
 wherein contacts of the second group of contacts include metallic pillars that extend through the redistribution layer to couple to respective contacts of the third group of contacts. 
   
     
     
         2 . The method of  claim 1 , wherein bonding contacts of the third group to respective contacts of the second group comprises bonding together copper pillars formed on both the contacts of the second group and the contacts of the third group. 
     
     
         3 . The method of  claim 1 , wherein the second semiconductor die includes at least one additional contact outside the third group of contacts, and further comprising bonding the additional contact to a contact on the redistribution layer. 
     
     
         4 . The method of  claim 1 , further comprising placing an underfall material between the second semiconductor die and the redistribution layer. 
     
     
         5 . The method of  claim 1 , further comprising forming an encapsulant material over the second semiconductor die. 
     
     
         6 . The method of  claim 1 , wherein at least one of the first and second groups of contacts comprises an array of contacts extending in both X and Y directions on the first semiconductor die. 
     
     
         7 . The method of  claim 1 , further comprising forming contact balls on contacts the redistribution layer. 
     
     
         8 . The method of  claim 7 , wherein contacts of the first group of contacts are coupled to respective contact balls through conductive paths formed in the redistribution layer. 
     
     
         9 . The method of  claim 1 , wherein the pitch of the second group of contacts is no more than approximately 70% of the pitch of the first group of contacts. 
     
     
         10 . The method of  claim 1 , wherein the pitch of the second group of contacts is no more than approximately 50% of the pitch of the first group of contacts. 
     
     
         11 . The method of  claim 1 , wherein the microelectronic device package is a fan-out package. 
     
     
         12 . The method of  claim 2 , wherein the copper pillars from the first and second groups of contacts are bonded together through use of a tin-silver (SnAg) layer. 
     
     
         13 . The method of  claim 2 , wherein the copper pillars from the second and third sets of contacts form no electrical connection within the redistribution layer. 
     
     
         14 . The method of  claim 1 , wherein the redistribution layer contains multiple layers of conductive traces. 
     
     
         15 . The method of  claim 14 , wherein the copper pillars of the second group of contacts form no electrical connection with conductive traces of the redistribution layer. 
     
     
         16 . A method of forming an electronic system, comprising:
 forming a microelectronic device, comprising,
 forming a molded structure over a first semiconductor die,
 wherein the die includes first and second groups of contacts, 
 wherein the contacts of each of the first and second groups are respectively arranged at first and second pitches, and 
 wherein the contacts of the second group are at a finer pitch than the contacts of the first group; 
 
 forming a redistribution layer over the first semiconductor die and at least a portion of the molded structure, wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and a molded component, wherein the molded component extends around the first semiconductor die; and 
 coupling a second semiconductor die to the first semiconductor die, the second semiconductor die on the opposite side of the redistribution layer from the first semiconductor die,
 wherein the second semiconductor die includes a third group of contacts arranged at the same pitch as the contacts the second group, and 
 wherein the second semiconductor die is coupled to the first semiconductor die at least in part by bonding contacts of the third group to respective contacts of the second group, and 
 wherein contacts of the second group of contacts include metallic pillars that extend through the redistribution layer to couple to respective contacts of the third group of contacts; and 
 
   coupling one or more components of the microelectronic device to at least one of a mass storage device and a network interface.   
     
     
         17 . The method of forming an electronic system of  claim 16 , wherein the second semiconductor device further comprises at least one additional contact outside the third group of contacts. 
     
     
         18 . The method of forming an electronic syste of c aim  17 , wherein the additional contact is coupled to a contact in the redistribution layer. 
     
     
         19 . The method of forming an electronic system of  claim 18 , wherein the additional contact is outside a footprint of the first semiconductor die. 
     
     
         20 . The method of forming an electronic system of  claim 16 , wherein at least one of the first and second groups of contacts comprises an array of contacts extending in both X and Y directions on the first semiconductor die.