Patch antennas stitched to systems in packages and methods of assembling same

Abstract

A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

1 . A semiconductor device, comprising:
 a transceiver die disposed in a molding mass;   a through-mold via that communicates through the molding mass including one end thereof emerging at a molding mass top surface level and the other end thereof emerging at a land side of the molding mass;   a redistribution layer (RDL) disposed on the molding mass top surface, wherein the RDL includes signal and ground traces;   a signal pad disposed in the RDL;   a signal line contacting the signal pad; and   a patch antenna and ground plane separated by an air gap, wherein the signal line passes through the ground plane and contacts the patch antenna.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the signal line is a copper signal line. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the signal line includes a bond wire. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the signal line is soldered to the patch antenna. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the signal line is welded to the patch antenna. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the patch antenna and ground plane are an integral structure. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the integral structure includes one or more folds. 
     
     
         8 . The semiconductor device of  claim 1 , further including a ball grid array on the land side of the molding mass. 
     
     
         9 . The semiconductor device of  claim 1 , further including one or more spacers within the air gap to maintain a distance between the patch antenna and the ground plane. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the spacer includes a length between 100 micrometer (μm) to 300 μm. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the spacer includes a length between 100 micrometer (μm) to 200 μm. 
     
     
         12 . The semiconductor device of  claim 9 , wherein the spacer includes a length between 201 micrometer (μm) to 300 μm. 
     
     
         13 . A semiconductor device, comprising:
 a transceiver die disposed in a molding mass;   a through-mold via that communicates through the molding mass including one end thereof emerging at a molding mass top surface level and the other end thereof emerging at a land side of the molding mass;   a redistribution layer (RDL) disposed on the molding mass top surface, wherein the RDL includes signal and ground traces;   a signal pad disposed in the RDL;   a bond wire contacting the signal pad; and   a patch antenna and ground plane, wherein the bond wire is soldered to the patch antenna.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the bond wire includes copper. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the patch antenna and ground plane are separated by an air gap. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the patch antenna and ground plane are an integral structure. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the integral structure includes one or more folds. 
     
     
         18 . The semiconductor device of  claim 13 , further including one or more spacers within the air gap to maintain a distance between the patch antenna and the ground plane. 
     
     
         19 . The semiconductor device of  claim 13 , further including a ball grid array on the land side of the molding mass.