Modified nitride spacer for solving charge retention issue in floating gate memory cell

Abstract

A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

What is claimed is:  
     
       1. A method of forming a modified nitride spacer in a floating gate memory cell comprising the steps of: 
       providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined;  
       forming a gate oxide layer over said substrate;  
       forming a polysilicon layer doped with a second conductive type of dopant over said gate oxide layer;  
       patterning said polysilicon layer to form a gate electrode having sidewalls over said gate oxide layer; then  
       performing first ion implant on said substrate using said gate electrode as a mask to form lightly doped source/drain regions; then  
       forming an oxide layer over said gate electrode; then  
       forming a nitride layer over said oxide layer; then  
       etching said silicon nitride layer to form nitride spacers on sidewalls of said gate electrode; and  
       performing second ion implant on said substrate using said nitride spacers as a mask to complete the forming of said source/drain regions.  
     
     
       2. The method of  claim 1 , wherein said forming said gate oxide layer is accomplished by thermal growth at a temperature between about 750 to 1000° C. 
     
     
       3. The method of  claim 1 , wherein said gate oxide layer has a thickness between about 70 to 120 Å. 
     
     
       4. The method of  claim 1 , wherein said forming said polysilicon layer is accomplished with silicon source SiH 4  using LPCVD at a temperature between about 400 to 800° C. 
     
     
       5. The method of  claim 1 , wherein said gate electrode has a thickness between about 1500 to 2500 Å. 
     
     
       6. The method of  claim 1 , wherein said performing said first ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 6  atoms/cm 2  and energy level between about 50 to 100 KeV. 
     
     
       7. The method of  claim 1 , wherein said oxide layer has a thickness between about 170 to 800 Å. 
     
     
       8. The method of  claim 1 , wherein said oxide layer comprises high-temperature oxide (HTO) performed at a temperature between about 400 to 800° C. 
     
     
       9. The method of  claim 1 , wherein said oxide layer comprises Plasma Enhanced PE-oxide. 
     
     
       10. The method of  claim 1 , wherein said forming said nitride layer is accomplished by reacting dichlorosilane (SiCl 2 H 2 ) with ammonia (NH 3 ) in an LPCVD at temperature range between about 500 to 900° C. 
     
     
       11. The method of  claim 1 , wherein the thickness of said nitride layer is between about 800 to 2000 Å. 
     
     
       12. The method of  claim 1 , wherein said etching is accomplished anisotropically. 
     
     
       13. The method of  claim 1 , wherein said performing said second ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms/cm 2  and energy level between about 50 to 100 KeV. 
     
     
       14. A method of forming a modified spacer in a floating gate memory cell comprising the steps of: 
       providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined;  
       forming a gate oxide layer over said substrate;  
       forming a polysilicon layer doped with a second conductive type of dopant over said gate oxide layer;  
       patterning said polysilicon layer to form a gate electrode having sidewalls over said gate oxide layer;  
       performing first ion implant on said substrate using said gate electrode as a mask to form lightly doped source/drain regions;  
       forming an oxide layer over said gate electrode;  
       etching said oxide layer to form oxide spacers on sidewalls of said gate electrode; and  
       performing second ion implant on said substrate using said oxide spacers as a mask to complete the forming of said source/drain regions.  
     
     
       15. The method of  claim 14 , wherein said forming said gate oxide layer is accomplished by thermal growth at a temperature between about 750 to 1000° C. 
     
     
       16. The method of  claim 14 , wherein said gate oxide layer has a thickness between about 70 to 120 Å. 
     
     
       17. The method of  claim 14 , wherein said forming said polysilicon layer is accomplished with silicon source SiH 4  using LPCVD at a temperature between about 400 to 800° C. 
     
     
       18. The method of  claim 14 , wherein said gate electrode has a thickness between about 1500 to 2500 Å. 
     
     
       19. The method of  claim 14 , wherein said performing said first ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms /cm 2  and energy level between about 50 to 100 KeV. 
     
     
       20. The method of  claim 14 , wherein said oxide layer has a thickness between about 170 to 800 Å. 
     
     
       21. The method of  claim 14 , wherein said oxide layer comprises high-temperature oxide (HTO) performed at a temperature between about 400 to 800° C. 
     
     
       22. The method of  claim 14 , wherein said oxide layer comprises Plasma Enhanced PE-oxide. 
     
     
       23. The method of  claim 14 , wherein said etching is accomplished anisotropically. 
     
     
       24. The method of  claim 14 , wherein said performing said second ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms /cm 2  and energy level between about 50 to 100 KeV.