P
US6936774B2ExpiredUtilityPatentIndex 93

Wiring substrate produced by transfer material method

Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Feb 9, 2000Filed: Oct 29, 2002Granted: Aug 30, 2005
Est. expiryFeb 9, 2020(expired)· nominal 20-yr term from priority
Inventors:SUGAYA YASUHIROKOMATSU SHINGOHIRANO KOICHINAKATANI SEIICHIMATSUOKA YASUYUKIASAHI TOSHIYUKIYAMASHITA YOSHIHISA
H10P 72/7432H10P 72/7424H10P 72/743H05K 3/20H05K 1/0306H05K 1/16H05K 1/162H05K 1/165H05K 1/167H05K 3/205H05K 3/4061H05K 3/4069H05K 2203/1461Y10T29/49213Y10T428/12486Y10T29/49179Y10T29/49208Y10T29/49149
93
PatentIndex Score
17
Cited by
64
References
15
Claims

Abstract

A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.

Claims

exact text as granted — not AI-modified
1. A wiring substrate comprising
 an electric insulating substrate,  
 a wiring pattern embedded in at least one principal plane of the electric insulating substrate by a transfer method by the use of a transfer material, and  
 at least one concave portion formed on the surface of the electric insulating substrate,  
 wherein the wiring pattern is formed at the bottom of the concave portion such that the surface of the wiring pattern is lower than the surface of the substrate at portion in the vicinity of the wiring pattern.  
 
   
   
     2. The wiring substrate according to  claim 1 , wherein a depth of the concave portion is 1 to 12 μm. 
   
   
     3. The wiring substrate according to  claim 1  or  2 , wherein the wiring pattern comprises a first metal layer and a second metal layer formed on the first metal layer. 
   
   
     4. The wiring substrate according to  claim 3 , wherein the second metal layer is a gold-plating layer. 
   
   
     5. The wiring substrate according to  claim 1  or  2 , further comprising a semiconductor device mounted on the wiring pattern, wherein the bump of the semiconductor device is flip-chip bonded on the wiring pattern by positioning the bump of the semiconductor device in the concave portion, and the bump is electrically connected to the wiring pattern. 
   
   
     6. The wiring substrate according to  claim 1 , wherein the electric insulating substrate is provided with a through hole filled with a conductive composition, and the wiring pattern is electrically connected to the conductive composition. 
   
   
     7. The wiring substrate according to  claim 1 , wherein the electric insulating substrate comprises an inorganic filler and a thermosetting resin composition, and has a through hole filled with a conductive composition. 
   
   
     8. The wiring substrate according to  claim 7 , wherein the inorganic filler comprises at least one inorganic filler selected from the group consisting of Al 2 O 3 , MgO, BN, AlN and SiO 2 , the content of the inorganic filler is 70 to 95 weight %, and the content of the thermosetting resin composition is 5 to 30 weight %. 
   
   
     9. The wiring substrate according to  claim 1 , wherein the electric insulating substrate is a reinforcer impregnated with a thermosetting resin, and the reinforcer is at least one selected from the group consisting of a woven fabric of a glass fiber, a non-woven fabric of a glass fiber, a woven fabric of a thermal resistant organic fiber and a non-woven fabric of a thermal resistant organic fiber. 
   
   
     10. The wiring substrate according to  claim 1 , wherein the electric insulating substrate is formed of a ceramic. 
   
   
     11. The wiring substrate according to  claim 10 , wherein the ceramic comprises at least one component selected from the group consisting of Al 2 O 3 , MgO, ZrO 2 , TiO 2 , SiO 2 , BeO, BN, CaO and glass, or a Bi—Ca—Nb—O containing ceramic. 
   
   
     12. A multi-layered wiring substrate in which a plurality of wiring substrates are laminated,
 wherein at least one layer has a wiring substrate according to  claim 1 .  
 
   
   
     13. The multi-layered wiring substrate according to  claim 12 , wherein at least one of the plurality of wiring substrates is a ceramic wiring substrate having an electric insulating substrate including a ceramic,
 at least one of the ceramic wiring substrates has a convex wiring pattern formed an at least one principal plane,  
 a wiring substrate laminated on the principal plane having the convex wiring pattern is a composite wiring substrate having an electric insulating substrate including a thermosetting resin composition, and  
 the convex wiring pattern is embedded in the principal plane of the composite wiring substrate.  
 
   
   
     14. The multi-layered wiring substrate according to  claim 12 , wherein at least two of the plurality of wiring substrates are ceramic wiring substrates having an electric insulating substrate including a ceramic,
 at least one of the ceramic wiring substrates comprises a ceramic material different from the ceramic material of the other ceramic wiring substrates, and  
 a wiring substrate having an electric insulating substrate including a thermosetting resin composition is placed between the ceramic wiring substrates each containing a different ceramic material.  
 
   
   
     15. The multi-layered wiring substrate according to  claim 12 , wherein at least a top layer and a bottom layer of the plurality of wiring substrates are composite substrates having an electric insulating substrate including a thermosetting resin composition, and an inside layer is a ceramic wiring substrate having an electric insulating substrate including a ceramic.

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