Double patterning mask set and method of forming thereof

Abstract

A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.

1. A double patterning mask set, comprising:
 a first mask having a first set of via patterns, the first set of via patterns comprising at least two via patterns arranged along a diagonal direction, each of the two via patterns having at least a truncated corner; 
 a second mask having a second set of via patterns, wherein the first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction. 
 
     
     
       2. The mask set of  claim 1 , wherein the truncated corners of the two via patterns are the closest corners between the two via patterns. 
     
     
       3. The mask set of  claim 1 , wherein a length of a cutting side of the truncated corner is between half width of the via pattern and 1/20 width of the via pattern. 
     
     
       4. The mask set of  claim 3 , wherein the length of the cutting side of the truncated corner is between ⅕ width of the via pattern and 1/10 width of the via pattern. 
     
     
       5. A method for forming semiconductors on a wafer by utilizing a double patterning mask set, the method comprising:
 providing a double patterning mask set having a first mask with a first set of via patterns and a second mask with a second set of via patterns, the first set of via patterns and the second set of via patterns interlacedly arranged along a horizontal direction and a vertical direction, and at least one of the sets of via patterns comprising a via pattern with a truncated corner; 
 utilizing the first mask to expose the wafer; and 
 utilizing the second mask to expose the wafer. 
 
     
     
       6. A method for forming a double patterning mask set, the method comprising:
 generating a via pattern array; 
 dividing the via pattern array into a first set of via patterns and a second set of via patterns, wherein the first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction, and are complementary to each other to form the via pattern array; 
 modifying the first set of via patterns and the second set of via patterns to form at least a truncated corner on at least a via pattern; and 
 forming the modified first set of via patterns on a first mask, and forming the modified second set of via patterns on a second mask. 
 
     
     
       7. The method of  claim 6 , further comprising performing optical proximity correction on the modified first set of via patterns and the modified second set of via patterns. 
     
     
       8. The method of  claim 7 , wherein performing optical proximity correction on the modified first set of via patterns and the modified second set of via patterns is performing optical proximity correction on the modified first set of via patterns and the modified second set of via patterns by utilizing optical models. 
     
     
       9. The method of  claim 6 , wherein a length of a cutting side of the truncated corner is between half width of the via pattern and 1/20 width of the via pattern. 
     
     
       10. The method of  claim 9 , wherein the length of the cutting side of the truncated corner is between ⅕ width of the via pattern and 1/10 width of the via pattern.