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US8778717B2ActiveUtilityPatentIndex 50

Local oxidation of silicon processes with reduced lateral oxidation

Assignee: HSIAO RU-SHANGPriority: Mar 17, 2010Filed: Mar 17, 2010Granted: Jul 15, 2014
Est. expiryMar 17, 2030(~3.7 yrs left)· nominal 20-yr term from priority
Inventors:HSIAO RU-SHANGLIN CHUNG-TECHENG NAI-WENLIAO YIN-KAIWU WEI CHUANG
H10P 30/225H10P 30/209H10P 30/204H10W 10/0125H10W 10/13H10P 30/21H10F 71/121H10F 30/221H10P 30/28Y02E10/547Y02P70/50
50
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Cited by
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References
17
Claims

Abstract

A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of forming an integrated circuit structure, the method comprising:
 implanting a p-type impurity into a p-well region of a silicon substrate to form a p-type region; 
 co-implanting oxygen into the p-well region of the silicon substrate to form an oxygen-implanted region, wherein a portion of the p-type region overlaps the oxygen-implanted region; 
 after the step of implanting and the step of co-implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region; and 
 forming a photo diode in the silicon substrate, with an n-type region of the photo diode laterally contacting the p-type region. 
 
     
     
       2. The method of  claim 1 , wherein the portion of the p-type region converted to the silicon oxide region is an upper portion of the p-type region, and a lower portion of the p-type region is not converted to the silicon oxide region. 
     
     
       3. The method of  claim 1 , wherein the p-type impurity is implanted into a p-well of the silicon substrate. 
     
     
       4. The method of  claim 1 , wherein the anneal is performed at a temperature between about 800° C. and about 1100° C. 
     
     
       5. The method of  claim 1 , wherein the anneal is performed for a duration between about 1 minute and about 100 minutes. 
     
     
       6. The method of  claim 1 , wherein the anneal is performed in a chamber with a partial pressure of oxygen between about 1E(−2) torrs and about 5E2 torrs. 
     
     
       7. The method of  claim 1 , wherein the p-type impurity is selected from the group consisting essentially of boron, aluminum, gallium, indium, and combinations thereof. 
     
     
       8. The method of  claim 1  further comprising forming a shallow trench isolation (STI) region comprising:
 forming a trench in the silicon substrate; and 
 filling the trench with a dielectric material to form the STI region. 
 
     
     
       9. The method of  claim 1  further comprising:
 before the step of implanting the p-type impurity, forming a mask layer over the silicon substrate, with an opening formed in the mask layer, wherein the p-type region is formed by implanting through the opening; and 
 after the step of performing the anneal, removing the mask layer. 
 
     
     
       10. The method of  claim 9 , wherein the step of co-implanting oxygen is performed through the opening in the mask layer. 
     
     
       11. A method of forming an integrated circuit structure, the method comprising:
 forming a mask over a p-well region of a silicon substrate; 
 patterning the mask to form an opening; 
 performing a co-implantation comprising:
 implanting a p-type impurity through the opening and into the p-well region of the silicon substrate to form a p-type region; and 
 implanting an oxygen-containing material through the opening and into the p-well region of the silicon substrate to form an oxygen-implanted region, wherein the p-type region has a bottom lower than a bottom of the oxygen-implanted region; 
 
 after the step of performing the co-implantation, performing an anneal to convert the oxygen-implanted region to a silicon oxide region; and 
 after the anneal, removing the mask. 
 
     
     
       12. The method of  claim 11  further comprising forming a photo diode in the silicon substrate, with an n-type region of the photo diode laterally contacting the p-type region. 
     
     
       13. A method of forming an integrated circuit structure, the method comprising:
 implanting a p-type impurity into a p-well region of a silicon substrate to form a p-type region; 
 implanting oxygen into a portion of the silicon substrate directly over the p-type region, wherein a same mask is used in the steps of implanting oxygen and the p-type impurity; 
 performing an oxidation process to a surface the portion of the silicon substrate comprising implanted oxygen to form a silicon oxide region; and 
 forming a photo diode in the silicon substrate, with an n-type region of the photo diode laterally contacting the p-type region. 
 
     
     
       14. The method of  claim 13 , wherein substantially an entirety of the silicon oxide region comprises the p-type impurity. 
     
     
       15. The method of  claim 13 , wherein the p-type impurity comprises boron. 
     
     
       16. The method of  claim 13 , wherein the p-type impurity is implanted before the step of performing the oxidation process. 
     
     
       17. The method of  claim 13  further comprising forming a shallow trench isolation (STI) region in the silicon substrate.

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