Systems and methods for post-bonding wafer edge seal

Abstract

A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.

What is claimed is: 
     
       1. A method for fabricating a semiconductor device, the method comprising:
 arranging a first substrate over a second substrate; 
 performing a wafer bonding process, wherein first regions between the first substrate and the second substrate are enclosed and second regions are exposed to atmosphere; 
 after performing the wafer bonding process, performing one or more processes on the exposed second regions, including a fill process that forms a fill material within the exposed second regions; and 
 after performing the one or more processes on the exposed second regions, applying an edge sealing material on the first substrate and the second substrate. 
 
     
     
       2. The method of  claim 1 , further comprising performing an edge trimming process on the first substrate prior to performing the wafer bonding process. 
     
     
       3. The method of  claim 1 , further comprising removing unwanted portions of the edge sealing material from the first substrate. 
     
     
       4. The method of  claim 1 , wherein the wafer bonding process forms a bond ring between the first and second substrates. 
     
     
       5. The method of  claim 1 , wherein the second region includes trench areas and pad areas. 
     
     
       6. The method of  claim 1 , wherein the first region includes an inside cavity. 
     
     
       7. The method of  claim 2 , wherein the edge trimming process removes a selected width from an outside portion of the first substrate. 
     
     
       8. The method of  claim 2 , wherein performing the one or more processes on the exposed second region includes performing a surface treatment. 
     
     
       9. The method of  claim 2 , wherein performing the one or more processes on the exposed second region includes performing an additional fill operation. 
     
     
       10. The method of  claim 1 , further comprising performing a grinding operation. 
     
     
       11. The method of  claim 1 , wherein the semiconductor device is a MEMS device. 
     
     
       12. The method of  claim 1 , wherein the first and second substrates are first and second semiconductor wafers, respectively. 
     
     
       13. A method for fabricating a semiconductor device, the method comprising:
 providing a semiconductor device having a first substrate bonded to a second substrate, wherein first regions between the first substrate and the second substrate are enclosed and second regions between the first substrate and the second substrate are exposed; and 
 performing a fill operation between the first substrate and the second substrate; and 
 applying an edge sealing material on the first substrate and the second substrate. 
 
     
     
       14. The method of  claim 13 , further comprising performing an edge trimming process on the first substrate before applying an edge sealing material. 
     
     
       15. The method of  claim 13 , wherein the second regions include trench areas. 
     
     
       16. The method of  claim 13 , wherein semiconductor device includes a MEMS device. 
     
     
       17. The method of  claim 13 , wherein the bonding process forms bond rings around the first regions. 
     
     
       18. The method of  claim 17 , wherein a bond ring circumscribes the first regions along a first axis and extends between opposing faces of the first and second substrates along a second axis to enclose the first regions and thereby define an inside cavity between the first and second substrates. 
     
     
       19. The method of  claim 13 , further comprising removing a portion of the edge sealing material from the first substrate. 
     
     
       20. The method of  claim 13 , wherein the first and second substrates are first and second semiconductor wafers, respectively.