Resistance variable memory structure and method of forming the same

Abstract

A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

What is claimed: 
     
       1. A memory element comprising:
 a first dielectric layer over a conductive structure, the first dielectric layer having a first top surface; 
 a first opening in the first dielectric layer extending to the conductive structure, the first opening having an interior sidewall surface; 
 a first electrode in the first opening in the first dielectric layer, wherein the first electrode extends from a bottom of the first opening on to sidewalls of the first opening; 
 a resistance variable layer disposed over the first electrode, the resistance variable layer extending from the first electrode along a bottom of the first opening on to the first electrode that extends along the sidewalls of the first opening; and 
 a second electrode over the resistance variable layer. 
 
     
     
       2. The memory element of  claim 1 , wherein the sidewalls have an interior angle in a range of about 92° to about 135′. 
     
     
       3. The memory element of  claim 1 , further comprising an electrical contact in contact with the second electrode. 
     
     
       4. The memory element of  claim 1 , wherein the resistance variable layer comprises a high-k dielectric material, a binary metal oxide or a transition metal oxide. 
     
     
       5. The memory element of  claim 1 , wherein the resistance variable layer is selectively configurable to form at least one conductive path between the first electrode and the second electrode. 
     
     
       6. The memory element of  claim 1 , wherein a surface of the resistance variable layer, a surface of the first electrode, and a surface of the second electrode are substantially coplanar to the first top surface of the first dielectric layer. 
     
     
       7. The memory element of  claim 1 , wherein the first dielectric layer is substantially oxygen-free. 
     
     
       8. A method of forming a resistance variable memory element, the method comprising:
 forming a first dielectric layer over a conductive structure, the first dielectric layer having a first top surface; 
 etching an opening in the first dielectric layer thereby exposing an area of the conductive structure, the opening having an interior sidewall surface; 
 depositing a first electrode material over the exposed area of the conductive structure, along the interior sidewall surface of the opening, and over the first top surface of the first dielectric layer; 
 depositing a resistance variable layer over the first electrode material; 
 depositing a second electrode material over the resistance variable layer, the second electrode material having a portion in the opening, wherein the portion has a second top surface below the first top surface of the first dielectric layer; 
 forming a second dielectric layer over the second electrode material; and 
 performing at least one polishing process to remove the second dielectric layer, the second electrode material, the resistance variable layer, and the first electrode material from above the first top surface of the first dielectric layer. 
 
     
     
       9. The method as in  claim 8 , wherein the first electrode material is selected from the group of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, Wn, Cu and combinations thereof. 
     
     
       10. The method as in  claim 9 , wherein the first electrode material is deposited using atomic layer deposition. 
     
     
       11. The method as in  claim 8 , wherein the resistance variable layer selected from the group of nickel oxide, aluminum oxide, tantalum oxide, molybdenum oxide or copper oxide. 
     
     
       12. The method as in  claim 11 , wherein the resistance variable layer is deposited using pulsed laser deposition. 
     
     
       13. The method as in  claim 8 , wherein the second electrode material is selected from the group of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, Wn, Cu and combinations thereof. 
     
     
       14. The method as in  claim 13 , wherein the first electrode material is deposited using one of atomic layer deposition, sputtering or physical vapor deposition. 
     
     
       15. The method as in  claim 8 , wherein the second dielectric layer comprises silicon nitride or silicon carbide. 
     
     
       16. The method as in  claim 15 , wherein the second dielectric layer is deposited using atomic layer deposition, chemical vapor deposition or plasma enhanced chemical vapor deposition. 
     
     
       17. The method as in  claim 8 , wherein the second dielectric layer is substantially oxygen free. 
     
     
       18. The method as in  claim 8 , wherein the at least one polishing process is chemical-mechanical polishing. 
     
     
       19. A method of forming a resistance variable memory element, the method comprising:
 forming a first dielectric layer over a conductive structure of a substrate, the first dielectric layer having a first top surface; 
 etching an opening in the first dielectric layer, thereby exposing an area of the conductive structure, the opening having an interior sidewall surface; 
 depositing a first electrode material over the exposed area of the conductive structure, along the interior sidewall surface of the opening, and over the first top surface of the first dielectric layer; 
 depositing a resistance variable layer comprising a high-K dielectric material, a binary metal oxide, and a transition metal oxide; 
 depositing a second electrode material over the resistance variable layer, the second electrode material having a portion in the opening, wherein the portion has a second top surface below the first top surface of the first dielectric layer; 
 forming a second dielectric layer over the second electrode material, wherein the second dielectric layer comprises silicon nitride and/or silicon carbide and is substantially oxygen free; 
 performing at least one polishing process to remove the second dielectric layer, the second electrode material, the resistance variable layer, and the first electrode material from above the first top surface of the first dielectric layer; and 
 forming a contact to the second electrode material. 
 
     
     
       20. The method as in  claim 19  wherein the second dielectric layer is substantially oxygen free.