Pillar bumps and process for making same

Abstract

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

What is claimed is: 
     
       1. A method comprising:
 forming input/output terminals for external connectors on one surface of a semiconductor substrate; 
 depositing a passivation layer on the input/output terminals; 
 patterning the passivation layer to form openings exposing a portion of the input/output terminals; 
 depositing a seed layer over the passivation layer; 
 depositing a photoresist layer on the seed layer; 
 developing the photoresist layer to form photoresist openings in the photoresist layer over the input/output terminals; 
 patterning a bottom portion of the photoresist openings to form bird's beak patterns at a bottom of the openings, the bird's beak patterns extending outwardly from the openings; and 
 forming a conductive material in the photoresist openings, 
 wherein the conductive material forms a pillar extending upwardly from the seed layer having an upper portion with a first width and a base portion with a second width that is greater than the first width. 
 
     
     
       2. The method of  claim 1 , wherein forming the conductive material comprises electroplating a conductive material using a low initial deposition rate to fill the bird's beak patterns with the conductive material. 
     
     
       3. The method of  claim 2 , wherein the low initial deposition rate comprises a rate between 0.1 and 0.5 amperes per decimeter squared. 
     
     
       4. The method of  claim 1 , wherein patterning the bottom portion of the photoresist openings comprises performing a wet clean process on the surface of the seed layer. 
     
     
       5. The method of  claim 1 , wherein patterning the bottom portion of the photoresist openings comprises plasma treating a top surface of the seed layer, the plasma treating being performed using a gas comprising nitrogen and hydrogen. 
     
     
       6. The method of  claim 1 , wherein patterning the bottom portion of the photoresist openings comprises performing a defocus process during development of the photoresist layer. 
     
     
       7. The method of  claim 1 , wherein forming the conductive material comprises performing an electrochemical plating process to plate copper. 
     
     
       8. A method comprising:
 forming input/output terminals for external connectors on one surface of a semiconductor substrate; 
 depositing a passivation layer on the input/output terminals; 
 patterning the passivation layer to form openings exposing a portion of the input/output terminals; 
 depositing a photoresist layer over the passivation layer; 
 developing the photoresist layer to form photoresist openings in the photoresist layer over the input/output terminals defining a base portion and an upper portion; 
 patterning a bottom portion of the photoresist openings to form bird's beak patterns at a bottom of the openings; and 
 forming a conductive material in the photoresist openings, 
 wherein the conductive material forms a pillar extending upwardly from the input/output terminals having an upper portion with a first width and a base portion overlying the passivation layer with a wider second width. 
 
     
     
       9. The method of  claim 8 , wherein developing the photoresist layer comprises performing defocus and energy exposure variations to create sloping sidewalls in the opening in the photoresist layer. 
     
     
       10. The method of  claim 8 , further comprising forming a solder material over the pillar. 
     
     
       11. The method of  claim 8 , further comprising electroplating a conductive material using a low initial deposition rate to fill the bird's beak patterns with the conductive material. 
     
     
       12. The method of  claim 8 , wherein patterning the bottom portion of the photoresist openings includes subjecting the photoresist layer to a dry etch process or a wet etch process. 
     
     
       13. The method of  claim 8 , wherein the step of forming a conductive material in the photoresist openings includes forming a barrier layer in the openings and forming a seed layer on the barrier layer. 
     
     
       14. The method of  claim 13 , further comprising removing an oxide from a top surface of the seed layer. 
     
     
       15. A method comprising:
 forming an terminal on a substrate; 
 covering the substrate with a passivation layer; 
 patterning the passivation layer to form an opening in the passivation layer having a first width, the opening in the passivation layer exposing the terminal; 
 depositing photoresist over the passivation layer and the exposed terminal; 
 patterning the photoresist to form a second opening over the exposed terminal, wherein the second opening has a top portion having a second width and a bottom portion having a third width wider than the second width, wherein the second width is wider than the first width, wherein patterning the photoresist to form a second opening over the exposed terminal includes:
 forming the second opening with substantially vertical sidewalls, and 
 processing the bottom portion of the photoresist to form a recess extending outward from a center of the second opening in the bottom portion; and 
 
 filling the opening in the passivation layer and the second opening with a conductor. 
 
     
     
       16. The method of  claim 15 , wherein patterning the photoresist for to form a second opening over the exposed terminal includes defocusing and varying an intensity of exposure energy during a process of exposing the photoresist to an exposure light. 
     
     
       17. The method of  claim 15 , wherein the bottom portion of the second opening has a trapezoidal shape when viewed in cross section. 
     
     
       18. The method of  claim 15 , further comprising depositing an under bump metallization (UBM) layer on the passivation layer. 
     
     
       19. The method of  claim 18 , further comprising:
 stripping the photoresist; 
 etching exposed portions of the UBM layer; and 
 forming a solder layer over the conductor. 
 
     
     
       20. The method of  claim 8 , further comprising:
 stripping the photoresist layer; and 
 forming a solder layer over the conductive material.