Forming grounded through-silicon vias in a semiconductor substrate

Abstract

A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

What is claimed is: 
     
       1. A method of forming a semiconductor device, comprising:
 providing a semiconductor substrate, the semiconductor substrate having a first side and a second side opposite the first side; 
 forming a through-silicon via (TSV) opening extending from the first side of the semiconductor substrate into the semiconductor substrate; 
 forming a liner layer on the first side of the semiconductor substrate and along the sidewalls and bottom of the TSV opening; 
 depositing a first conductive material layer over the liner layer in the opening to form a TSV; 
 forming an inter-layer dielectric (ILD) layer over the first side of the semiconductor substrate; 
 forming a via opening extending from the ILD layer into a portion of the semiconductor substrate; 
 forming a trench opening in the ILD layer to expose a portion of the TSV; and 
 depositing a second conductive material layer in the via and the trench openings to form an interconnect structure, the interconnect structure electrically connecting the TSV with the semiconductor substrate. 
 
     
     
       2. The method of  claim 1 , wherein the semiconductor device is an interposer. 
     
     
       3. The method of  claim 1 , after the forming the TSV, further comprising planarizing the first side of the semiconductor substrate. 
     
     
       4. The method of  claim 1 , further comprising forming a first barrier layer between the liner layer and the TSV. 
     
     
       5. The method of  claim 4 , further comprising forming a first seed layer between the first barrier layer and the TSV. 
     
     
       6. The method of  claim 1 , before the forming the ILD layer over the first side of the semiconductor substrate, further comprising forming an etch stop layer. 
     
     
       7. The method of  claim 1 , further comprising forming a second barrier layer over the via and trench openings. 
     
     
       8. The method of  claim 7 , further comprising forming a second seed layer over the second barrier layer. 
     
     
       9. The method of  claim 1 , wherein the interconnect structure is formed by electro-chemical plating. 
     
     
       10. The method of  claim 1 , wherein the TSV and interconnect structure comprise copper or copper alloys. 
     
     
       11. The method of  claim 1 , after the forming the interconnect structure, further comprising planarizing the first side of the semiconductor substrate. 
     
     
       12. A method of forming an interposer, comprising:
 providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; 
 forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; 
 forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and 
 forming an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the second partition has straight sidewalls extending from the first partition to a bottom of the second partition and wherein the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate. 
 
     
     
       13. The method of  claim 12 , further comprising forming a liner layer between at least the one or more TSVs and the semiconductor substrate. 
     
     
       14. The method of  claim 13 , further comprising forming a barrier layer and/or a seed layer between the one or more TSVs and the liner layer. 
     
     
       15. The method of  claim 12 , further comprising forming a barrier layer and/or seed layer between at least the interconnect structure and the ILD layer and the front surface of the semiconductor substrate. 
     
     
       16. An integrated circuit structure, comprising:
 a semiconductor substrate having a front surface and a back surface opposite the front surface; 
 a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate; and 
 an interconnect structure having a first partition and a second partition, the first partition formed in an inter-layer dielectric (ILD) layer, the ILD layer overlying the front surface of the semiconductor substrate, and the second partition formed in a portion of the semiconductor substrate and having straight sidewalls from a top surface of the semiconductor substrate to a bottom surface of the second partition, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate. 
 
     
     
       17. The integrated circuit structure of  claim 16 , wherein the integrated circuit structure is an interposer. 
     
     
       18. The integrated circuit structure of  claim 16 , further comprising a liner layer formed at least between the TSV and the semiconductor substrate. 
     
     
       19. The integrated circuit structure of  claim 18 , further comprising:
 a barrier layer formed between the TSV and the liner layer; and 
 a seed layer formed between the TSV and the barrier layer. 
 
     
     
       20. The integrated circuit structure of  claim 16 , wherein the interconnect structure and the TSV are formed of the same conductive material. 
     
     
       21. The integrated circuit structure of  claim 17 , wherein the interposer comprises passive devices. 
     
     
       22. The integrated circuit structure of  claim 21 , wherein the interposer comprises active devices. 
     
     
       23. An interposer, comprising:
 a semiconductor substrate having a front surface and a back surface opposite the front surface; 
 a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate; 
 a liner layer formed at least between the TSV and the semiconductor substrate; 
 an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate; and 
 an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate and wherein the second partition has straight sidewalls as the second partition extends into the semiconductor substrate to a bottom surface of the second partition. 
 
     
     
       24. The interposer of  claim 23 , further comprising a barrier layer formed between the TSV and the liner layer. 
     
     
       25. The interposer of  claim 24 , further comprising a seed layer formed between the TSV and the barrier layer. 
     
     
       26. The interposer of  claim 23 , wherein the interconnect structure and the TSV are formed of the same conductive material. 
     
     
       27. The interposer of  claim 23 , further comprising passive devices. 
     
     
       28. The interposer of  claim 27 , further comprising active devices. 
     
     
       29. A semiconductor package structure, comprising:
 an interposer having: 
 a semiconductor substrate having a front surface and a back surface opposite the front surface; 
 a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate; 
 a liner layer formed at least between the TSV and the semiconductor substrate; 
 an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate; and 
 an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate, wherein a straight sidewall of the second partition extends from a bottom of the second partition to a surface of the semiconductor substrate facing the first partition; 
 a semiconductor chip; and 
 a plurality of bonding pads bonding the semiconductor chip to the interposer. 
 
     
     
       30. The semiconductor package structure of  claim 29 , further comprising an additional semiconductor chip bonded onto the semiconductor chip. 
     
     
       31. The semiconductor package structure of  claim 29 , wherein the interposer comprises passive devices. 
     
     
       32. The semiconductor package structure of  claim 31 , wherein the interposer further comprises active devices. 
     
     
       33. A semiconductor package structure, comprising:
 an interposer having: 
 a semiconductor substrate having a front surface and a back surface opposite the front surface; 
 a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate; 
 a liner layer formed at least between the TSV and the semiconductor substrate; 
 an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate; and 
 an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate, the second partition having a straight sidewall through the semiconductor substrate; 
 a multi-chip semiconductor structure having at least a first chip and a second chip; and 
 a plurality of bonding pads bonding the multi-chip semiconductor structure to the interposer. 
 
     
     
       34. The semiconductor package structure of  claim 33 , wherein the interposer comprises passive devices. 
     
     
       35. The semiconductor package structure of  claim 34 , wherein the interposer further comprises active devices. 
     
     
       36. An integrated circuit structure, comprising:
 a semiconductor substrate having a front surface and a back surface opposite the front surface;   a through via (TV) formed in the semiconductor substrate;   a liner layer formed at least between the TV and the semiconductor substrate; and   an interconnect structure having a first partition and a second partition, the first partition formed in an inter-layer dielectric (ILD) layer, the ILD layer overlying the front surface of the semiconductor substrate, and the second partition formed with straight sidewalls in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TV to the semiconductor substrate.   
     
     
       37. The integrated circuit structure of claim 36, wherein the integrated circuit structure is an interposer. 
     
     
       38. The integrated circuit structure of claim 36, further comprising: a first barrier layer formed between the TV and the liner layer; and a seed layer formed between the TV and the first barrier layer. 
     
     
       39. The integrated circuit structure of claim 38, wherein the interconnect structure comprises a second barrier layer. 
     
     
       40. The integrated circuit structure of claim 39, wherein the second barrier layer is in contact with a top surface of TV. 
     
     
       41. The integrated circuit structure of claim 39, wherein the second barrier layer is in contact with the first barrier layer. 
     
     
       42. The integrated circuit structure of claim 36, wherein the interconnect structure and the TV are formed of the same conductive material. 
     
     
       43. The integrated circuit structure of claim 37, wherein the interposer comprises passive devices. 
     
     
       44. The integrated circuit structure of claim 43, wherein the interposer comprises active devices. 
     
     
       45. The integrated circuit structure of claim 36, wherein the TV is grounded. 
     
     
       46. The integrated circuit structure of claim 36, further comprising another TV in the semiconductor substrate and being insulated from the semiconductor substrate by the liner layer. 
     
     
       47. The integrated circuit structure of claim 36, wherein the liner layer located between the ILD layer and the front surface of the semiconductor substrate is conformal. 
     
     
       48. An interposer, comprising:
 a semiconductor substrate having a front surface and a back surface opposite the front surface;   a through via (TV) formed in the semiconductor substrate;   a liner layer formed at least between the TV and the semiconductor substrate;   an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate;   an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TV to the semiconductor substrate, wherein the second partition has straight sidewalls within the semiconductor substrate.   
     
     
       49. The interposer of claim 48, further comprising a first barrier layer formed between the TV and the liner layer. 
     
     
       50. The interposer of claim 49, further comprising a seed layer formed between the TV and the first barrier layer. 
     
     
       51. The integrated circuit structure of claim 49, wherein the second liner comprises a second barrier layer. 
     
     
       52. The integrated circuit structure of claim 51, wherein the second barrier layer is in contact with a top surface of TV. 
     
     
       53. The integrated circuit structure of claim 51, wherein the second barrier layer is in contact with the first barrier layer. 
     
     
       54. The interposer of claim 48, wherein the interconnect structure and the TV are formed of the same conductive material. 
     
     
       55. The interposer of claim 48, further comprising passive devices. 
     
     
       56. The interposer of claim 55, further comprising active devices. 
     
     
       57. The integrated circuit structure of claim 48, wherein the TV is grounded. 
     
     
       58. The integrated circuit structure of claim 48, further comprising another TV in the semiconductor substrate and being insulated from the semiconductor substrate by the liner layer. 
     
     
       59. The integrated circuit structure of claim 48, wherein the liner layer comprises a portion between the ILD layer and the front surface of the semiconductor substrate. 
     
     
       60. A semiconductor package structure, comprising:
 an interposer having:   a semiconductor substrate having a front surface and a back surface opposite the front surface;   a through via (TV) formed in the semiconductor substrate;   a liner layer formed at least between the TV and the semiconductor substrate;   a dielectric layer formed over the front surface of the semiconductor substrate; and an interconnect structure having a first partition and a second partition, the first partition formed in the dielectric layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TV to the semiconductor substrate, the second partition extends into the semiconductor substrate a first length, the second partition having a straight sidewall along the first length; and   a semiconductor chip bonded to the interposer.   
     
     
       61. The semiconductor package structure of claim 60, further comprising an additional semiconductor chip bonded onto the semiconductor chip. 
     
     
       62. The semiconductor package structure of claim 60, wherein the interposer comprises passive devices. 
     
     
       63. The semiconductor package structure of claim 62, wherein the interposer further comprises active devices. 
     
     
       64. The integrated circuit structure of claim 60, wherein the semiconductor chip is bonded to the interposer through a plurality of bonding pads. 
     
     
       65. The integrated circuit structure of claim 60, wherein the TV is grounded. 
     
     
       66. The integrated circuit structure of claim 60, further comprising another TV in the semiconductor substrate and being insulated from the semiconductor substrate by the liner layer. 
     
     
       67. The integrated circuit structure of claim 60, wherein the liner layer comprises a portion between the dielectric layer and the front surface of the semiconductor substrate. 
     
     
       68. A semiconductor package structure, comprising:
 an interposer having:
 a semiconductor substrate having a front surface and a back surface opposite the front surface; 
 a through via (TV) in the semiconductor substrate; 
 a liner layer formed at least between the TV and the semiconductor substrate; 
 a dielectric layer formed over the front surface of the semiconductor substrate; and 
 an interconnect structure having a first partition and a second partition, the first partition formed in the dielectric layer and the second partition formed with straight sidewalls extending into a portion of the semiconductor substrate, the straight sidewalls extending from a first side of the second partition to a second side of the second partition opposite the first side of the partition, wherein the interconnect structure electrically connects the TV to the semiconductor substrate; and 
   a multi-chip semiconductor structure having at least a first chip and a second chip, wherein at least one of the first chip and the second chip is bonded to the interposer.   
     
     
       69. The semiconductor package structure of claim 68, wherein the interposer comprises passive devices. 
     
     
       70. The semiconductor package structure of claim 69, wherein the interposer further comprises active devices. 
     
     
       71. The integrated circuit structure of claim 68, wherein the first chip is bonded to the interposer through a plurality of bonding pads. 
     
     
       72. The integrated circuit structure of claim 68, wherein the TV is grounded. 
     
     
       73. The integrated circuit structure of claim 68, further comprising another TV in the semiconductor substrate and being insulated from the semiconductor substrate by the liner layer. 
     
     
       74. The integrated circuit structure of claim 68, wherein the second chip is bonded onto the first chip.