Semiconductor package

Abstract

A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

What is claimed is: 
     
       1. A method for manufacturing a semiconductor package, comprising:
 forming a redistribution substrate; and 
 placing a semiconductor chip on the redistribution substrate, 
 wherein the forming a redistribution substrate includes, 
 forming an under-bump pattern, 
 forming a first photo-imageable dielectric layer including a preliminary via hole exposing the under-bump pattern on the under-bump pattern, 
 forming a first hard mask layer covering the first photo-imageable dielectric layer and the under-bump pattern, wherein the first hard mask partially fills the preliminary via hole, 
 etching the first hard mask layer and the first photo-imageable dielectric layer sequentially to remove the first hard mask layer in the preliminary via hole and form a via hole from the preliminary via hole and a first hole vertically overlapping and connecting with the via hole, 
 removing the first hard mask layer, 
 forming a first seed/barrier layer and a first metal layer sequentially to fill the via hole and the first hole, and 
 performing a planarization process on the first seed/barrier layer and the first metal layer to form a redistribution pattern. 
 
     
     
       2. The method for manufacturing a semiconductor package according to  claim 1 , wherein
 the etching includes placing a first mask pattern including a first opening vertically overlapping the preliminary via hole on the first hard mask layer, and 
 a diameter of the first opening is larger than a diameter of the preliminary via hole. 
 
     
     
       3. The method for manufacturing a semiconductor package according to  claim 1 , wherein the first hard mask layer comprises a metal material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, and tungsten. 
     
     
       4. The method for manufacturing a semiconductor package according to  claim 1 , wherein etching the first hard mask layer includes an anisotropic etching process. 
     
     
       5. The method for manufacturing a semiconductor package according to  claim 1 , wherein the removing includes a wet etching process. 
     
     
       6. The method for manufacturing a semiconductor package according to  claim 1 , further comprising:
 forming a trench connected to the first hole when sequentially etching the first hard mask layer and the first photo-imageable dielectric layer, 
 wherein the trench extends in a line shape, and a diameter of the first hole is larger than a width of the trench. 
 
     
     
       7. The method for manufacturing a semiconductor package according to  claim 1 , further comprising:
 forming a first trench separated from the first hole when sequentially etching the first hard mask layer and the first photo-imageable dielectric layer, 
 wherein the first trench extends in a line shape, and a diameter of the first hole is larger than a width of the first trench. 
 
     
     
       8. The method for manufacturing a semiconductor package according to  claim 7 , wherein a depth of the first hole is greater than a depth of the first trench. 
     
     
       9. The method for manufacturing a semiconductor package according to  claim 7 , wherein the first trench has convex sidewalls when viewed from a side. 
     
     
       10. The method for manufacturing a semiconductor package according to  claim 7 , wherein a level of a center of a bottom surface of the first trench is higher than a level of an edge of the bottom surface. 
     
     
       11. The method for manufacturing a semiconductor package according to  claim 7 , further comprising:
 forming a second trench separated from the first hole and the first trench when sequentially etching the first hard mask layer and the first photo-imageable dielectric layer, 
 wherein the second trench extends in a line shape, and a width of the second trench is larger than the width of the first trench. 
 
     
     
       12. The method for manufacturing a semiconductor package according to  claim 11 , wherein a depth of the second trench is greater than a depth of the first trench. 
     
     
       13. The method for manufacturing a semiconductor package according to  claim 1 , wherein the forming an under bump pattern includes:
 preparing a carrier substrate; 
 forming an adhesive layer on the carrier substrate; 
 forming a second photo-imageable dielectric layer on the adhesive layer; 
 forming a second hard mask layer on the second photo-imageable dielectric layer; 
 forming a second mask pattern on the second hard mask layer; 
 using the second mask pattern as an etching mask to form a second opening penetrating the second photo-imageable dielectric layer; 
 forming a second seed/barrier layer and a second metal layer successively on the second photo-imageable dielectric layer and the adhesive layer, filling the second opening; and 
 performing a planarization process on the second seed/barrier layer and the second metal layer. 
 
     
     
       14. A method for manufacturing a semiconductor package, comprising:
 forming a redistribution substrate; and 
 placing a semiconductor chip on the redistribution substrate, 
 wherein the forming a redistribution substrate includes, 
 forming a photo-imageable dielectric layer, 
 forming a hard mask layer on the photo-imageable dielectric layer, 
 forming a mask pattern on the hard mask layer, including a first opening and a second opening, 
 anisotropically etching the hard mask layer and the photo-imageable dielectric layer to fully remove the hard mask layer exposed by the mask pattern and form a first trench and a second trench vertically overlapping with the first opening and the second opening, respectively, 
 removing the hard mask layer and the mask pattern, 
 successively forming a seed/barrier layer and a metal layer on the photo-imageable dielectric layer, filling the first trench and the second trench, and 
 planarizing the seed/barrier layer and the metal layer, 
 wherein a width of the second opening is larger than that of the first opening. 
 
     
     
       15. The method for manufacturing a semiconductor package according to  claim 14 , wherein the anisotropically etching includes at least one of a reactive ion etching (RIE), magnetically enhanced reactive ion etching (MERIE), inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, hollow anode type plasma etching, or helical resonator plasma etching process. 
     
     
       16. The method for manufacturing a semiconductor package according to  claim 14 , wherein a depth of the first trench is larger than a depth of the second trench. 
     
     
       17. The method for manufacturing a semiconductor package according to  claim 14 , wherein sidewalls of the first trench and the second trench have a laterally convex shape. 
     
     
       18. The method for manufacturing a semiconductor package according to  claim 14 , wherein the first trench has a maximum width between a top or a bottom, and the first trench has a minimum width at the top or at the bottom. 
     
     
       19. The method for manufacturing a semiconductor package according to  claim 14 , wherein a level of a bottom surface of the first trench is higher than a level of a bottom surface of the second trench. 
     
     
       20. The method for manufacturing a semiconductor package according to  claim 19 , wherein a difference between the level of the bottom surface of the first trench and the level of the bottom surface of the second trench is more than 0 and less than 0.5 μm.