US2006214237A1PendingUtilityA1
Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
Est. expiryJun 30, 2024(expired)· nominal 20-yr term from priority
H10P 10/00H10D 84/0181H10D 84/0172H10D 84/038
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Claims
Abstract
Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.
Claims
exact text as granted — not AI-modified1 . an integrated circuit comprising:
a substrate; and an NMOS transistor and a PMOS transistor, said NMOS and PMOS transistors formed on said substrate, said NMOS transistor and said PMOS transistor forming a complementary metal oxide semiconductor structure, said NMOS transistor and said PMOS transistor having different gate dielectrics, one of said transistors having a gate dielectric with a dielectric constant greater than 10 and the other of said transistors having a gate dielectric with a dielectric constant of less than 10.
2 . The circuit of claim 1 wherein said dielectrics have different dielectric thicknesses.
3 . The circuit of claim 1 wherein said dielectrics are formed of different dielectric materials.
4 . The circuit of claim 1 wherein said dielectrics are formed by different techniques.
5 . The circuit of claim 1 wherein said dielectrics are covered by metal gate electrodes.
6 . The circuit of claim 1 wherein said NMOS transistor has a gate dielectric with a larger conduction band offset.
7 . The circuit of claim 1 wherein said PMOS transistor has a gate dielectric with a higher dielectric constant.
8 . The circuit of claim 1 wherein the gate dielectric of said NMOS transistor is thicker than the gate dielectric of said PMOS transistor.Join the waitlist — get patent alerts
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