Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Abstract

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si 1-x Ge x . The highest layer may be of the form Si 1-y Ge y on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si 1-z Ge z on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

1 . A method comprising:
 forming a PMOS transistor having both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress, including a first layer under said gate electrode of Si 1-y Ge y  and a second layer under said first layer, said second layer having Si 1-x Ge x  where x is less than y.   
   
   
       2 . The method of  claim 1  including forming a substrate covered by a first layer having an increasing concentration of germanium extending upwardly through the layer. 
   
   
       3 . The method of  claim 2  including covering said first layer with a second layer of constant germanium concentration. 
   
   
       4 . The method of  claim 3  including forming a source and drain of epitaxial silicon germanium of the form Si 1-z Ge z . 
   
   
       5 . The method of  claim 4  including making z greater than x and x less than y. 
   
   
       6 . The method of  claim 1  including forming uniaxial compressive stress in the channel direction by forming a silicon germanium epitaxial source drain. 
   
   
       7 . The method of  claim 1  including forming in-plane biaxial compressive stress by depositing a silicon germanium layer as a channel having the form Si 1-y Ge y  and forming an underlying buffer layer of the form Si 1-x Ge x  where x is less than y. 
   
   
       8 . The method of  claim 1  including forming NMOS and PMOS transistors at the same time. 
   
   
       9 . The method of  claim 8  including forming a graded germanium concentration silicon germanium buffer layer, covering said buffer layer with a layer of silicon germanium of constant germanium concentration, and covering said constant germanium concentration layer with a tensile strained silicon layer on both the NMOS and PMOS sides. 
   
   
       10 . The method of  claim 9  including selectively removing the tensile strained biaxial silicon layer on the PMOS side. 
   
   
       11 . The method of  claim 10  including selectively removing the tensile strained silicon layer using about 5 to 8 percent NH 4 OH with a pH between about 10.2 and 10.4 at a temperature between about 20° C. and 27° C. 
   
   
       12 . The method of  claim 10  including removing said tensile strained silicon layer on the PMOS side using an etchant that solubilizes the tensile strained silicon layer but does not solubilize underlying layers having higher germanium concentrations.