Fabrication of channel wraparound gate structure for field-effect transistor

Abstract

A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

1 . A transistor structure, comprising:
 a semiconductor body disposed on a substrate;   source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and   a gate stack comprising a gate insulation material and a conductive gate material, the gate stack completely surrounding the channel region of the semiconductor body, wherein a portion of the gate stack between the semiconductor body and the substrate comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.   
     
     
         2 . The transistor structure defined by  claim 1 , wherein the semiconductor body is disposed on an insulator layer of the substrate. 
     
     
         3 . The transistor structure defined by  claim 2 , wherein the portion of the gate stack between the semiconductor body and the substrate is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity. 
     
     
         4 . The transistor structure defined by  claim 3 , wherein the portion of the gate stack between the semiconductor body and the substrate only partially fills the cavity to provide a void in the layer of the conductive gate material of the portion of the gate stack between the semiconductor body and the substrate. 
     
     
         5 . The transistor structure defined by  claim 3 , wherein the portion of the gate stack between the semiconductor body and the substrate completely fills the cavity. 
     
     
         6 . The transistor structure defined by  claim 1 , wherein the gate insulation material comprises a high-k dielectric layer. 
     
     
         7 . The transistor structure defined by  claim 1 , wherein the conductive gate material comprises a metal and has a work function between 3.9 to 5.2 eV. 
     
     
         8 . A transistor structure, comprising:
 a semiconductor body disposed on a substrate and having a top surface, a bottom surface, a first side surface and a second side surface;   source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions;   a first gate electrode disposed on the top surface of the semiconductor body and comprising a gate insulation material and a conductive gate material;   a second gate electrode disposed on the first side surface of the semiconductor body and comprising the gate insulation material and the conductive gate material;   a third gate electrode disposed on the second side surface of the semiconductor body and comprising the gate insulation material and the conductive gate material; and   a fourth gate electrode disposed on the bottom surface of the semiconductor body and comprising the gate insulation material and the conductive gate material, the fourth gate electrode comprising a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.   
     
     
         9 . The transistor structure defined by  claim 8 , wherein the semiconductor body is disposed on an insulator layer of the substrate. 
     
     
         10 . The transistor structure defined by  claim 9 , wherein the fourth gate electrode is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity. 
     
     
         11 . The transistor structure defined by  claim 10 , wherein the fourth gate electrode only partially fills the cavity to provide a void in the layer of the conductive gate material of the fourth gate electrode. 
     
     
         12 . The transistor structure defined by  claim 10 , wherein the fourth gate electrode completely fills the cavity. 
     
     
         13 . The transistor structure defined by  claim 8 , wherein the gate insulation material comprises a high-k dielectric layer. 
     
     
         14 . The transistor structure defined by  claim 8 , wherein the conductive gate material comprises a metal and has a work function between 3.9 to 5.2 eV. 
     
     
         15 . A transistor structure, comprising:
 a semiconductor body disposed on a substrate and having a top surface, a bottom surface, and a pair of side surfaces;   source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and   a gate stack comprising a gate insulation material and a conductive gate material, the gate stack disposed on the entire top surface, the entire side surfaces, and at least a portion of the bottom surface of the semiconductor body, wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.   
     
     
         16 . The transistor structure defined by  claim 15 , wherein the semiconductor body is disposed on an insulator layer of the substrate. 
     
     
         17 . The transistor structure defined by  claim 16 , wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity. 
     
     
         18 . The transistor structure defined by  claim 17 , wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body only partially fills the cavity to provide a void in the conductive gate material of the portion of the gate stack disposed on the bottom surface of the semiconductor body. 
     
     
         19 . The transistor structure defined by  claim 17 , wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body completely fills the cavity. 
     
     
         20 . The transistor structure defined by  claim 16 , wherein a portion of the insulator layer of the substrate is disposed between a portion of the portion of the gate stack disposed on the bottom surface of the semiconductor body.