Recessed channel array transistor (rcat) in replacement metal gate (rmg) logic flow

Abstract

Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.

1 - 20 . (canceled) 
     
     
         21 . An apparatus, comprising:
 a first gate bounded on opposing sides thereof by spacers on a first substrate region of a substrate, wherein the first gate comprises a first conformal high-k dielectric layer adjacent the spacers and a portion of the substrate between the spacers, and a first gate metal adjacent the first conformal high-k dielectric layer; and   a second gate bound on opposing sides thereof by spacers on a second substrate region of the substrate, wherein the second gate comprises a second conformal high-k dielectric layer adjacent the spacers and extending into a recessed channel formed in the substrate below the position of the second gate, and a second gate metal adjacent the second conformal high-k dielectric layer;   wherein the second gate metal is a different gate metal from the first gate metal.   
     
     
         22 . The apparatus of  claim 21 , wherein the first conformal high-k dielectric layer is different from the second conformal high-k dielectric layer. 
     
     
         23 . The apparatus of  claim 21 , wherein the first conformal high-k dielectric layer has a different thickness from the second conformal high-k dielectric layer. 
     
     
         24 . The apparatus of  claim 21 , wherein the first gate of the first substrate region comprises a logic transistor. 
     
     
         25 . The apparatus of  claim 21 , wherein the second gate of the second substrate region comprises an analog transistor. 
     
     
         26 . The apparatus of  claim 21 , wherein the second gate of the second substrate region comprises a memory transistor. 
     
     
         27 . The apparatus of  claim 21 , wherein the second gate of the second substrate region comprises a recessed channel transistor (RCAT) having an effective gate length longer than a layout gate length. 
     
     
         28 . The apparatus of  claim 21 , wherein the first gate metal includes an implanted dopant. 
     
     
         29 . The apparatus of  claim 21 , wherein the second gate metal includes an implanted dopant. 
     
     
         30 . An apparatus, comprising:
 a first gate bounded on opposing sides thereof by spacers on a first substrate region of a substrate, wherein the first gate comprises a first conformal high-k dielectric layer adjacent the spacers and a portion of the substrate between the spacers, and a first gate metal adjacent the first conformal high-k dielectric layer; and   a second gate bound on opposing sides thereof by spacers on a second substrate region of the substrate, wherein the second gate comprises a second conformal high-k dielectric layer adjacent the spacers and extending into a recessed channel formed in the substrate below the position of the second gate, and a second gate metal adjacent the second conformal high-k dielectric layer;   wherein the first conformal high-k dielectric layer is a different high-k dielectric layer from the second conformal high-k dielectric layer.   
     
     
         31 . The apparatus of  claim 30 , wherein the first gate metal is different from the second gate metal. 
     
     
         32 . The apparatus of  claim 30 , wherein the first conformal high-k dielectric layer has a different thickness from the second conformal high-k dielectric layer. 
     
     
         33 . The apparatus of  claim 30 , wherein the first gate of the first substrate region comprises a logic transistor. 
     
     
         34 . The apparatus of  claim 30 , wherein the second gate of the second substrate region comprises an analog transistor. 
     
     
         35 . The apparatus of  claim 30 , wherein the second gate of the second substrate region comprises a memory transistor. 
     
     
         36 . The apparatus of  claim 30 , wherein the second gate of the second substrate region comprises a recessed channel transistor (RCAT) having an effective gate length longer than a layout gate length. 
     
     
         37 . The apparatus of  claim 30 , wherein the first gate metal includes an implanted dopant. 
     
     
         38 . The apparatus of  claim 30 , wherein the second gate metal includes an implanted dopant.