US2013119532A1PendingUtilityA1

Bumps for Chip Scale Packaging

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Assignee: LIN CHUN-HUNGPriority: Nov 11, 2011Filed: Nov 11, 2011Published: May 16, 2013
Est. expiryNov 11, 2031(~5.3 yrs left)· nominal 20-yr term from priority
Inventors:Chun-Hung LinYu-Feng ChenTsung-Shu LinHan-Ping PuHsien-Wei Chen
H10W 72/926H10W 72/9445H10W 72/936H10W 72/29H10W 72/9232H10W 72/942H10W 72/934H10W 72/923H10W 72/01938H10W 72/01935H10W 70/69H10W 70/66H10W 70/60H10W 72/07236H10W 72/072H10W 72/241H10W 90/724H10W 72/07253H10W 72/237H10W 72/227H10W 72/248H10W 72/252H10W 72/244H10W 72/242H10W 20/49H10W 74/137H10W 74/129
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Claims

Abstract

A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

Claims

exact text as granted — not AI-modified
1 . A device comprising:
 a semiconductor die;   a first bump having a first diameter on a first region of the semiconductor die; and   a second bump having a second diameter on a second region of the semiconductor die, wherein the second diameter is different from the first diameter.   
     
     
         2 . The device of  claim 1 , wherein the first diameter is greater than the second diameter. 
     
     
         3 . The device of  claim 1 , wherein:
 the first region is an inner region of the semiconductor die; and   the second region is an outer region of the semiconductor die.   
     
     
         4 . The device of  claim 3 , wherein the outer region has a width approximately equal to or less than one third of a width of the inner region. 
     
     
         5 . The device of  claim 4 , wherein:
 the first region is an inner region of the semiconductor die; and   the second region is a corner of the semiconductor die.   
     
     
         6 . The device of  claim 1 , wherein:
 the first bump is formed on a first under bump metal structure; and   the second bump is formed on a second under bump metal structure, wherein the first under bump metal structure is different from the second under bump metal structure.   
     
     
         7 . The device of  claim 6 , wherein the second under bump metal structure has a diameter greater than a diameter of the first under bump metal structure. 
     
     
         8 . A device comprising:
 a semiconductor die;   a first bump having a first diameter and a first height formed adjacent to an edge of the semiconductor die; and   a second bump having a second diameter and a second height formed not adjacent to the edge of the semiconductor die, wherein the second bump is different from the first bump.   
     
     
         9 . The device of  claim 8 , wherein the second diameter is greater than the first diameter. 
     
     
         10 . The device of  claim 8 , wherein the first height is greater than the second height. 
     
     
         11 . The device of  claim 8 , wherein:
 the first bump is formed on an outer region of the semiconductor die; and   the second bump is formed on an inner region of the semiconductor die.   
     
     
         12 . The device of  claim 11 , wherein the outer region has a width approximately equal to or less than one third of a width of the inner region. 
     
     
         13 . The device of  claim 8 , wherein:
 the first bump is formed on a first corner of the semiconductor die; and   the second bump is formed on an inner region of the semiconductor die.   
     
     
         14 . The device of  claim 8 , wherein the semiconductor die comprises:
 a substrate;   an interlayer dielectric layer formed on the substrate;   a plurality of metallization layers formed over the interlayer dielectric layer;   a passivation layer formed over the plurality of metallization layers; and   a polymer layer formed on the passivation layer, wherein a redistribution layer is formed in the polymer layer.   
     
     
         15 . A structure comprising:
 a semiconductor die;   a first under bump metal structure having a first diameter formed on an outer region of the semiconductor die; and   a second under bump metal structure having a second diameter formed on an inner region of the semiconductor die, wherein the first under bump metal structure is different from the second under bump metal structure.   
     
     
         16 . The structure of  claim 15 , wherein the second diameter is greater than the first diameter. 
     
     
         17 . The structure of  claim 15 , wherein the outer region has a width approximately equal to or less than one third of a width of the inner region. 
     
     
         18 . The structure of  claim 15 , further comprising:
 a first bump formed on the first under bump metal structure; and   a second bump formed on the second under metal structure.   
     
     
         19 . The structure of  claim 18 , wherein:
 the first bump is thinner than the second bump; and   the first bump is of an hourglass shape.   
     
     
         20 . The structure of  claim 15 , wherein the semiconductor die comprises:
 a substrate;   an interlayer dielectric layer formed on the substrate;   a plurality of metallization layers formed over the interlayer dielectric layer;   a passivation layer formed over the plurality of metallization layers; and   a polymer layer formed on the passivation layer, wherein a redistribution layer is formed in the polymer layer.

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