Package-on-package interconnect stiffener

Abstract

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

1 . A package-on-package (PoP) assembly, comprising:
 a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and   a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.   
     
     
         2 . The assembly of  claim 1 , wherein the stiffener includes routing features accommodating various circuitry designs of the second package. 
     
     
         3 . The assembly of  claim 2 , wherein the substrate includes a coefficient of thermal expansion (CTE) approximately between 15 and 25 ppm, and a flexural modulus approximately between 15 and 30 GPa. 
     
     
         4 . The assembly of  claim 1 , wherein the layout of the second plurality of planar contact pads of the stiffener matches the layout of the inter-package contact pads of the first package. 
     
     
         5 . The assembly of  claim 1 , wherein the stiffener includes a plug material disposed between the first plurality and the second plurality of planar contact pads. 
     
     
         6 . The assembly of  claim 1 , wherein the stiffener includes a plug material disposed in the substrate. 
     
     
         7 . A method to form a package-on-package (PoP) assembly, comprising:
 providing a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   attaching micro balls to the inter-package contact pads of the first package;   connecting a planar stiffener to the micro balls attached to the first package, the stiffener having a first plurality of planar contact pads on the top side of the stiffener to receive a second semiconductor package, and a second plurality of planar contact pads to connect the stiffener to the micro balls attached to the first package; and   reflowing the micro balls to form electrical connection between the stiffener and the first package.   
     
     
         8 . The method of  claim 7 , further comprising attaching a bottom side of the stiffener to the first package by way of an adhesive of low glass transition temperature (T g ). 
     
     
         9 . The method of  claim 7 , wherein the stiffener comprises:
 a substrate having a through recess adapted to house a die attached to the first package, and a plurality of through openings through which the first and second pluralities of contact pads are disposed;   a solder-wettable planar surface finish on the first and second pluralities of contact pads; and   a conductive trace electrically connecting the first plurality of contact pads to the corresponding second plurality of contact pads.   
     
     
         10 . A semiconductor assembly, comprising:
 a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package and a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the planar stiffener;   wherein the second die and the planar stiffener are stacked on the first substrate.   
     
     
         11 . The semiconductor assembly of  claim 10 , wherein the planar stiffener is configured to electrically connect a second semiconductor package including the planar stiffener and the second die. 
     
     
         12 . The semiconductor assembly of  claim 10 , wherein the second die is part of a memory package. 
     
     
         13 . The semiconductor assembly of  claim 10 , wherein the second die is part of a cache unit. 
     
     
         14 . The semiconductor assembly of  claim 10 , wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package. 
     
     
         15 . The semiconductor assembly of  claim 10 , wherein the first die is part of a semiconductor logic package. 
     
     
         16 . The semiconductor assembly of  claim 10 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package. 
     
     
         17 . The semiconductor assembly of  claim 10 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit. 
     
     
         18 . The semiconductor assembly of  claim 10 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package. 
     
     
         19 . The semiconductor assembly of  claim 10 , wherein the wire bond is electrically coupled to the planar stiffener by direct contact to a second substrate upon which the second die is disposed. 
     
     
         20 . The semiconductor assembly of  claim 10 , wherein the first semiconductor package is attachable to a motherboard via the second level interconnect pads. 
     
     
         21 . A semiconductor assembly, comprising:
 a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   a stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package and   a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the stiffener;   wherein the second die and the stiffener are stacked on the first substrate;   wherein the stiffener is configured to electrically connect a second semiconductor package including the stiffener and the second die; and   wherein the second die is part of a memory package.   
     
     
         22 . The semiconductor assembly of  claim 21 , wherein the wire bond is electrically coupled to the stiffener by direct contact to a second substrate upon which the second die is disposed. 
     
     
         23 . A semiconductor assembly, comprising:
 a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   a stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package;   a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the stiffener;   wherein the second die and the stiffener are stacked on the first substrate;   wherein the stiffener is configured to electrically connect a second semiconductor package; and   wherein the second die is part of a memory package; and   wherein the first semiconductor package and the stiffener are electrically coupled through a micro ball.   
     
     
         24 . The semiconductor assembly of  claim 23 , wherein the first die is part of a semiconductor logic package. 
     
     
         25 . The semiconductor assembly of  claim 23 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package. 
     
     
         26 . The semiconductor assembly of  claim 23 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit. 
     
     
         27 . The semiconductor assembly of  claim 23 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package. 
     
     
         28 . The semiconductor assembly of  claim 23 , wherein the wire bond is electrically coupled to the stiffener by direct contact to a second substrate upon which the second die is disposed. 
     
     
         29 . A semiconductor assembly, comprising:
 a first semiconductor package including a first die and a first substrate having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect to a second semiconductor package, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package; and   a wire bond that that is wire-bonded to a die in the second semiconductor package.   
     
     
         30 . The semiconductor assembly of  claim 29 , wherein the second die is part of a memory package. 
     
     
         31 . The semiconductor assembly of  claim 29 , wherein the second die is part of a cache unit. 
     
     
         32 . The semiconductor assembly of  claim 29 , wherein the second die is part of a device package suited for connection with the type of device of the first package. 
     
     
         33 . The semiconductor assembly of  claim 29 , wherein the first die is part of a semiconductor logic package. 
     
     
         34 . The semiconductor assembly of  claim 29 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package. 
     
     
         35 . The semiconductor assembly of  claim 29 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit. 
     
     
         36 . The semiconductor assembly of  claim 29 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first package. 
     
     
         37 . A semiconductor assembly, comprising:
 a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;   a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect a second semiconductor package including the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package; and   a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the planar stiffener; wherein the second die and the planar stiffener are stacked on the first substrate.   
     
     
         38 . The semiconductor assembly of  claim 37 , wherein the second die is part of a memory package. 
     
     
         39 . The semiconductor assembly of  claim 37 , wherein the second die is part of a cache unit. 
     
     
         40 . The semiconductor assembly of  claim 37 , wherein the second die is part of a device package suited for connection with the type of device of the first package. 
     
     
         41 . The semiconductor assembly of  claim 37 , wherein the first die is part of a semiconductor logic package. 
     
     
         42 . The semiconductor assembly of  claim 37 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package. 
     
     
         43 . The semiconductor assembly of  claim 37 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit. 
     
     
         44 . The semiconductor assembly of  claim 37 , wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first package.