Semiconductor devices having through-vias and methods for fabricating the same

Abstract

A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate comprising a first surface and an opposed, second surface, the substrate extending in a horizontal direction of extension;   an insulation layer on the first surface of the substrate;   a conductive via extending through the substrate in a vertical direction of extension relative to the horizontal direction of extension of the substrate, a first end of the conductive via extending through the first surface of the substrate so that the first end protrudes in the vertical direction relative to the first surface of the substrate; and   an alignment key recess in the insulation layer at a side of, and spaced apart from, the conductive via, an outermost edge of the alignment key recess having a rounded cross-sectional profile.   
     
     
         2 . The semiconductor device of  claim 1  further comprising a conductive terminal pad on the first end of the conductive via. 
     
     
         3 . The semiconductor device of  claim 1  wherein the insulation layer comprises a lower insulation layer on the first surface of the substrate and an upper insulation layer on the lower insulation layer, wherein the lower insulation layer and the upper insulation layer have different etch selectivities with respect to each other, and wherein the alignment key recess is in the upper insulation layer. 
     
     
         4 . The semiconductor device of  claim 3  wherein the alignment key recess comprises a partial recess in the upper insulation layer. 
     
     
         5 . The semiconductor device of  claim 3  wherein the alignment key recess comprises a complete recess in the upper insulation layer. 
     
     
         6 . The semiconductor device of  claim 3  wherein the alignment key recess comprises a complete recess in the upper insulation layer and a partial recess in the lower insulation layer. 
     
     
         7 . The semiconductor device of  claim 3  wherein the lower insulation layer extends from the first surface of the substrate along a sidewall of the conductive via. 
     
     
         8 . The semiconductor device of  claim 3  further comprising a via insulation layer between sidewalls of the conductive via. 
     
     
         9 . The semiconductor device of  claim 1  wherein the semiconductor device comprises first and second stacked semiconductor devices, and wherein the conductive via of the first semiconductor device and the conductive via of the second semiconductor device are connected at a conductive terminal. 
     
     
         10 . The semiconductor device of  claim 9  wherein the conductive terminal is aligned between the conductive via of the first semiconductor device and the conductive via of the second semiconductor device. 
     
     
         11 . The semiconductor device of  claim 9  wherein the conductive terminal is horizontally offset so that it is not aligned between the conductive via of the first semiconductor device and the conductive via of the second semiconductor device. 
     
     
         12 . A memory system comprising:
 a memory controller that generates command and address signals; and   a memory module comprising a plurality of memory devices, the memory module receiving the command and address signals and in response storing and retrieving data to and from at least one of the memory devices,
 wherein each memory device comprises:
 a substrate comprising a first surface and an opposed, second surface, the substrate extending in a horizontal direction of extension; 
 an insulation layer on the first surface of the substrate; 
 a conductive via extending through the substrate in a vertical direction of extension relative to the horizontal direction of extension of the substrate, a first end of the conductive via extending through the first surface of the substrate so that the first end protrudes in the vertical direction relative to the first surface of the substrate; and 
 an alignment key recess in the insulation layer at a side of, and spaced apart from, the conductive via, an outermost edge of the alignment key recess having a rounded cross-sectional profile.