Fabrication of channel wraparound gate structure for field-effect transistor

Abstract

A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor body above a substrate, the semiconductor body having a top surface, a pair of sidewalls, and a bottom;   a gate electrode haying a first portion over a portion of the top surface of the semiconductor body, a second portion adjacent a portion of the sidewalls of the semiconductor body, and a third portion below the bottom surface of the semiconductor body, wherein the first portion of the gate electrode is continuous with the second portion of the gate electrode, and wherein the third portion of the gate electrode is continuous with the second portion of the gate electrode;   a gate dielectric layer between the first portion of the gate electrode and the portion of the top surface of the semiconductor body, between the second portion of the gate electrode and the portion of the sidewalls of the semiconductor body, and between the third portion of the gate electrode and the bottom surface of the semiconductor body, Wherein is continuous around a top surface, sidewall surfaces and a bottom surface of the third portion of the gate electrode;   an insulating layer above the substrate and laterally adjacent to the third portion of the gate electrode;   a source region at a first side of the gate electrode; and   a drain region at a second side of the gate electrode opposite the first side of the gate electrode.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the insulating layer is laterally adjacent to a portion of the gate dielectric layer between the third portion of the gate electrode and the bottom surface of the semiconductor body. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the third portion of the gate electrode comprises a void surrounded by a top portion, sidewall portions and a bottom portion of the third portion of the gate electrode. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the third portion of the gate electrode is void-free. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV. 
     
     
         8 . A method of fabricating a semiconductor structure, the method comprising:
 forming a semiconductor body above a substrate, the semiconductor body having a top surface, a pair of sidewalls, and a bottom;   forming a gate electrode having a first portion over a portion of the top surface of the semiconductor body, a second portion adjacent a portion of the sidewalls of the semiconductor body, and a third portion below the bottom surface of the semiconductor body, wherein the first portion of the gate electrode is continuous with the second portion of the gate electrode, and wherein the third portion of the gate electrode is continuous with the second portion of the gate electrode;   forming a gate dielectric layer between the first portion of the gate electrode and the portion of the top surface of the semiconductor body, between the second portion of the gate electrode and the portion of the sidewalls of the semiconductor body, and between the third portion of the gate electrode and the bottom surface of the semiconductor body, wherein is continuous around a top surface, sidewall surfaces and a bottom surface of the third portion of the gate electrode;   forming an insulating layer above the substrate and laterally adjacent to the third portion of the gate electrode forming a source region at a first side of the gate electrode; and   forming a drain region at a second side of the gate electrode opposite the first side of the gate electrode.   
     
     
         9 . The method of  claim 8 , wherein the insulating layer is laterally adjacent to a portion of the gate dielectric layer between the third portion of the gate electrode and the bottom surface of the semiconductor body. 
     
     
         10 . The method of  claim 8 , wherein the third portion of the gate electrode comprises a void surrounded by a top portion, sidewall portions and a bottom portion of the third portion of the gate electrode. 
     
     
         11 . The method of  claim 8 , wherein the third portion of the gate electrode is void-free. 
     
     
         12 . The method of  claim 8 , wherein the gate dielectric layer comprises a high-k dielectric material. 
     
     
         13 . The method of  claim 12 , wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV. 
     
     
         14 . The method of  claim 8 , wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV.