Methods and apparatus for wafer-level packaging using direct writing

Abstract

A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure.

1 . A method of forming a semiconductor structure on a wafer, comprising:
 depositing a polymer layer on the wafer in a wafer-level packaging process;   forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to; and   removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure.   
     
     
         2 . The method of  claim 1 , wherein the direct writing process is a two-photon polymerization process. 
     
     
         3 . The method of  claim 2 , wherein the two-photon polymerization process uses a femtosecond laser in combination with a pair of galvanometric laser scanners. 
     
     
         4 . The method of  claim 1 , wherein the wafer has at least one semiconductor device on a surface of the wafer before depositing the polymer layer. 
     
     
         5 . The method of  claim 1 , wherein the at least one wafer-level packaging structure is a high-aspect ratio structure with an aspect ratio of greater than approximately 5:1. 
     
     
         6 . The method of  claim 5 , wherein the high-aspect ratio structure is part of three-dimensional metal-insulator-metal capacitor. 
     
     
         7 . The method of  claim 5 , wherein the high-aspect ratio structure is a heat sink. 
     
     
         8 . The method of  claim 1 , wherein the at least one wafer-level packaging structure is at least partially hollow. 
     
     
         9 . The method of  claim 1 , wherein the at least one wafer-level packaging structure is a coil. 
     
     
         10 . The method of  claim 9 , wherein the coil is part of a three-dimensional toroidal inductor. 
     
     
         11 . The method of  claim 1 , wherein the at least one wafer-level packaging structure is an interconnect. 
     
     
         12 . A method of forming a semiconductor structure on a wafer, comprising:
 depositing a polymer layer on the wafer in a wafer-level packaging process, wherein the wafer has at least one semiconductor chip on a surface of the wafer;   forming at least one wafer-level packaging structure in the polymer layer using a two-photon polymerization process that solidifies portions of the polymer layer; and   removing portions of the polymer layer that have not been solidified by the two-photon polymerization process revealing the at least one wafer-level packaging structure.   
     
     
         13 . The method of  claim 12 , wherein the two-photon polymerization process uses a femtosecond laser in combination with a pair of galvanometric laser scanners. 
     
     
         14 . The method of  claim 12 , wherein the at least one wafer-level packaging structure is a high-aspect ratio structure with an aspect ratio of greater than approximately 5:1. 
     
     
         15 . The method of  claim 14 , wherein the high-aspect ratio structure is part of three-dimensional metal-insulator-metal capacitor. 
     
     
         16 . The method of  claim 14 , wherein the high-aspect ratio structure is a heat sink. 
     
     
         17 . The method of  claim 12 , wherein the at least one wafer-level packaging structure is at least partially hollow. 
     
     
         18 . The method of  claim 12 , wherein the at least one wafer-level packaging structure is at least one coil of a three-dimensional toroidal inductor. 
     
     
         19 . The method of  claim 12 , wherein the at least one wafer-level packaging structure is an interconnect. 
     
     
         20 . A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for forming a semiconductor structure to be performed, the method comprising:
 depositing a polymer layer on a wafer in a wafer-level packaging process, wherein the wafer has at least one semiconductor chip on a surface of the wafer;   forming at least one wafer-level packaging structure in the polymer layer using a two-photon polymerization process that solidifies portions of the polymer layer; and   removing portions of the polymer layer that have not been solidified by the two-photon polymerization process revealing the at least one wafer-level packaging structure.