3D Integrated Circuit and Methods of Forming the Same

Abstract

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate; and   a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer,   wherein the first and second bonding layers are in contact with each other, and   wherein each of the first and second adsorption layers includes a low-k dielectric material.   
     
     
         2 . The semiconductor structure according to  claim 1 , further comprising:
 a first insulating interlayer between the first substrate and the first adsorption layer; and   a second insulating interlayer on the second adsorption layer.   
     
     
         3 . The semiconductor structure according to  claim 2 , wherein the conductive pattern structure at least partially penetrates into each of the first and second insulating interlayers. 
     
     
         4 . The semiconductor structure according to  claim 1 , wherein the first adsorption layer is a first porous dielectric layer. 
     
     
         5 . The semiconductor structure according to  claim 4 , wherein the first porous dielectric layer has a porosity between about 5 percent and about 40 percent. 
     
     
         6 . The semiconductor structure according to  claim 5 , wherein the second adsorption layer is a second porous dielectric layer. 
     
     
         7 . The semiconductor structure according to  claim 6 , wherein the second porous dielectric layer has a porosity between about 5 percent and about 40 percent. 
     
     
         8 . A semiconductor structure comprising:
 a first adsorption layer and a first bonding layer stacked on a substrate;   a first conductive pattern penetrating through the first adsorption layer and the first bonding layer;   a second bonding layer and a second adsorption layer stacked on the first bonding layer; and   a second conductive pattern penetrating through the second bonding layer and the second adsorption layer,   wherein the first bonding layer and the second bonding layer are in contact with each other, and the first conductive pattern and the second conductive pattern are in contact with each other, and   wherein each of the first adsorption layer and the second adsorption layer comprises a low-k dielectric material.   
     
     
         9 . The semiconductor structure according to  claim 8 , further comprising:
 a first insulating interlayer between the substrate and the first adsorption layer; and   a second insulating interlayer on the second adsorption layer.   
     
     
         10 . The semiconductor structure according to  claim 9 , wherein the first conductive pattern at least partially penetrates into each of the first insulating interlayer and the second insulating interlayer. 
     
     
         11 . The semiconductor structure according to  claim 8 , wherein the first adsorption layer comprises fluorine-doped silicate glass. 
     
     
         12 . The semiconductor structure according to  claim 8 , wherein the first conductive pattern has straight sidewalls. 
     
     
         13 . The semiconductor structure according to  claim 8 , wherein the first conductive pattern comprises copper. 
     
     
         14 . The semiconductor structure according to  claim 8 , wherein the first bonding layer comprises silicon oxynitride. 
     
     
         15 . A semiconductor structure comprising:
 a first dielectric layer and a first bonding layer stacked on a substrate, the first dielectric layer comprising a first porous dielectric material;   a first conductive pattern penetrating through the first dielectric layer and the first bonding layer;   a second bonding layer and a second dielectric layer stacked on the first bonding layer and the first conductive pattern, the second dielectric layer comprising a second porous dielectric material; and   a second conductive pattern penetrating through the second bonding layer and the second dielectric layer, wherein the first bonding layer and the second bonding layer are in contact with each other, and the first conductive pattern and the second conductive patterns are in contact with each other.   
     
     
         16 . The semiconductor structure according to  claim 15 , further comprising:
 a first insulating interlayer between the substrate and the first dielectric layer; and   a second insulating interlayer on the second dielectric layer.   
     
     
         17 . The semiconductor structure according to  claim 16 , further comprising an etch stop layer between the first insulating interlayer and the substrate. 
     
     
         18 . The semiconductor structure according to  claim 17 , wherein the etch stop layer comprises silicon carbide. 
     
     
         19 . The semiconductor structure according to  claim 15 , wherein the first porous dielectric material has a porosity between about 5 percent and about 40 percent. 
     
     
         20 . The semiconductor structure according to  claim 15 , wherein the first conductive pattern at least partially penetrates into each of the first insulating interlayer and the second insulating interlayer.