US2023395463A1PendingUtilityA1

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Assignee: MICRON TECHNOLOGY INCPriority: Jul 14, 2014Filed: Aug 23, 2023Published: Dec 7, 2023
Est. expiryJul 14, 2034(~8 yrs left)· nominal 20-yr term from priority
H10W 90/736H10W 90/734H10W 90/732H10W 90/724H10W 90/722H10W 90/297H10W 90/288H10W 74/10H10W 72/07354H10W 72/07339H10W 72/07254H10W 72/07252H10W 72/01225H10W 72/952H10W 72/884H10W 72/877H10W 72/856H10W 72/354H10W 72/353H10W 72/347H10W 72/325H10W 72/267H10W 72/265H10W 72/253H10W 72/252H10W 72/247H10W 72/244H10W 72/227H10W 72/225H10W 72/073H10W 72/072H10W 95/00H10W 90/00H10W 76/15H10W 76/12H10W 76/05H10W 74/117H10W 74/15H10W 74/012H10W 72/071H10W 40/258H10W 40/22H10W 99/00H10W 72/30H10W 72/20H10W 40/30H01L 23/44H01L 25/50H01L 21/563H01L 24/83H01L 23/3675H01L 25/18H01L 23/04H01L 21/50H01L 24/13H01L 24/16H01L 24/17H01L 24/32H01L 24/92H01L 25/0657H01L 23/3736H01L 24/73H01L 21/52H01L 21/54H01L 23/053H01L 23/3128H01L 2924/156H01L 2924/1815H01L 2224/1703H01L 2224/32145H01L 2224/73203H01L 2224/73253H01L 2225/06517H01L 2225/06589H01L 2924/1431H01L 2924/1434H01L 2924/16235H01L 2924/16251H01L 2225/06513H01L 2225/06541H01L 2224/17519H01L 2224/2939H01L 24/29H01L 24/33H01L 2224/1134H01L 2224/13025H01L 2224/131H01L 2224/13111H01L 2224/13147H01L 2224/13155H01L 2224/133H01L 2224/16145H01L 2224/16146H01L 2224/16227H01L 2224/17181H01L 2224/2919H01L 2224/29191H01L 2224/2929H01L 2224/29393H01L 2224/32225H01L 2224/32245H01L 2224/33181H01L 2224/73204H01L 2224/73265H01L 2224/83101H01L 2224/83102H01L 2224/83424H01L 2224/83447H01L 2224/8388H01L 2224/92125H01L 2924/15311H01L 2224/83104H01L 2224/1329
81
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Claims

exact text as granted — not AI-modified
I/We claim: 
     
         1 . A method of packaging a semiconductor die assembly having a first semiconductor die coupled to a package substrate and a plurality of second semiconductor dies arranged in a stack on the first semiconductor die, wherein the first semiconductor die has a peripheral region extending laterally outward from the stack of second semiconductor dies, the method comprising:
 attaching a sidewall of a thermal transfer structure to the peripheral region of the first semiconductor die, wherein the sidewall extends to a height equal to or greater than an elevation of an uppermost one of the second semiconductor dies in the stack, and wherein the sidewall extends around a perimeter of the stack of the second semiconductor dies;   depositing an underfill material around the second semiconductor dies; and   attaching a top of the thermal transfer structure to the sidewall of the thermal transfer structure, wherein the sidewall and the top of the thermal transfer structure together define a cavity that encloses the stack of the second semiconductor dies.   
     
     
         2 . The method of  claim 1  wherein the method further comprises attaching the sidewall of the thermal transfer structure to the package substrate. 
     
     
         3 . The method of  claim 1  wherein depositing the underfill material comprises depositing the underfill material into contact with an interior surface of the sidewall. 
     
     
         4 . The method of  claim 1  wherein depositing the underfill material comprises depositing the underfill material such that the underfill material has a fillet positioned between the sidewall and the stack of the second semiconductor dies. 
     
     
         5 . The method of  claim 1  wherein attaching the sidewall of the thermal transfer structure to the peripheral region of the first semiconductor die comprises attaching the sidewall such that sidewall is spaced apart from the stack of the second semiconductor dies by a gap. 
     
     
         6 . The method of  claim 5  wherein depositing the underfill material comprises depositing the underfill material into the gap. 
     
     
         7 . The method of  claim 1  wherein attaching the top of the thermal transfer structure to the sidewall of the thermal transfer structure comprises attaching the top to the sidewall via a thermal interface material. 
     
     
         8 . The method of  claim 1  wherein attaching the top of the thermal transfer structure to the sidewall of the thermal transfer structure further comprises attaching the top to the uppermost one of the second semiconductor dies via a thermal interface material. 
     
     
         9 . The method of  claim 1  wherein the top of the thermal transfer structure has a generally constant thickness in a direction orthogonal to the package substrate. 
     
     
         10 . A method of packaging a semiconductor die assembly having a first semiconductor die coupled to a package substrate and a plurality of second semiconductor dies arranged in a stack on the first semiconductor die, wherein the first semiconductor die has a peripheral region extending laterally outward from the stack of second semiconductor dies, the method comprising:
 attaching a foundation of a first portion of a thermal transfer structure to the package substrate and a shoulder of the first portion of the thermal transfer structure to the peripheral region of the first semiconductor die such that (a) the first portion surrounds a perimeter of the first semiconductor die and (b) an upper surface of the first portion is positioned at a height equal to or greater than an elevation of an uppermost one of the second semiconductor dies in the stack;   depositing an underfill material around the second semiconductor dies; and   attaching a second portion of the thermal transfer structure to the upper surface of the first portion of the thermal transfer structure to enclose the second semiconductor dies in a cavity defined by the first portion and the second portion of the thermal transfer structure.   
     
     
         11 . The method of  claim 10  wherein depositing the underfill material around the second semiconductor dies comprises depositing the underfill material through an opening defined in the upper surface of the first portion of the thermal transfer structure. 
     
     
         12 . The method of  claim 10  wherein the second portion of the thermal transfer structure has a generally constant thickness in a direction orthogonal to the package substrate. 
     
     
         13 . The method of  claim 10  wherein attaching the foundation of the first portion of the thermal transfer structure to the package substrate and the shoulder of the first portion of the thermal transfer structure to the peripheral region of the first semiconductor die comprises attaching the shoulder such that an inner surface of the first portion faces and surrounds the stack of the second semiconductor dies, and wherein depositing the underfill material comprises depositing the underfill material such that the underfill material contacts at least a portion of the inner surface of the first portion. 
     
     
         14 . The method of  claim 13  wherein the inner surface extends generally orthogonal to the first semiconductor die. 
     
     
         15 . The method of  claim 10  wherein depositing the underfill material comprises depositing the underfill material such that the underfill material has a fillet positioned between the first portion of the thermal transfer structure and the stack of the second semiconductor dies. 
     
     
         16 . The method of  claim 10  wherein the method further comprises attaching the second portion of the thermal transfer structure to the uppermost one of the second semiconductor dies in the stack. 
     
     
         17 . The method of  claim 10  wherein the upper surface of the first portion is positioned at a height equal to the elevation of the uppermost one of the second semiconductor dies in the stack. 
     
     
         18 . The method of  claim 10  wherein the first portion and the second portion of the thermal transfer structure are formed from a metal. 
     
     
         19 . A method of packaging a semiconductor die assembly having a first semiconductor die coupled to a package substrate and a plurality of second semiconductor dies arranged in a stack on the first semiconductor die, wherein the first semiconductor die has a peripheral region extending laterally outward from the stack of second semiconductor dies, the method comprising:
 attaching a base of a thermal structure to the package substrate and the peripheral region of the first semiconductor die such that (a) the base surrounds a perimeter of the first semiconductor die and (b) an upper surface of the base is positioned at a height equal to or greater than an elevation of an uppermost one of the second semiconductor dies in the stack;   depositing an underfill material, through an opening defined in the upper surface of the base, around the second semiconductor dies; and   attaching a cover of the thermal transfer structure to the upper surface of the base of the thermal transfer structure to enclose the second semiconductor dies in a cavity defined by the base and the cover of the thermal transfer structure.   
     
     
         20 . The method of  claim 19  wherein attaching the base of the thermal transfer structure to the package substrate and the peripheral region of the first semiconductor die comprises attaching the base such that an inner surface of the base faces and surrounds the stack of the second semiconductor dies, and wherein depositing the underfill material comprises depositing the underfill material such that the underfill material has a fillet (a) positioned between the stack of the second semiconductor dies and the inner surface and (b) that contacts at least a portion of the inner surface.

Join the waitlist — get patent alerts

Track US2023395463A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.