Three-dimensional memory devices and methods for forming the same

Abstract

A semiconductor device includes a peripheral circuit, a stacked structure including a first side and a second side along a vertical direction, and alternating conductive layers and first insulating layers, a memory string extending through the stacked structure, a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit, a second insulating layer located at the second side of the stacked structure; and a conductor structure located in the second insulating layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a peripheral circuit;   a stacked structure comprising a first side and a second side along a vertical direction, and comprising alternating conductive layers and first insulating layers;   a memory string extending through the stacked structure;   a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit;   a second insulating layer located at the second side of the stacked structure; and   a conductor structure located in the second insulating layer.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising
 a substrate located on a side of the peripheral circuit far from the bonding structure; and   a semiconductor layer located between the second side of the stacked structure and the second insulating layer, wherein the memory string is in contact with the semiconductor layer.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the conductor structure comprises a first conductor structure and a second conductor structure spaced apart a lateral direction. 
     
     
         4 . The semiconductor device of  claim 3 , wherein
 the first conductor structure comprises a first surface and a second surface along the vertical direction, and the first surface is close to the semiconductor layer relative to the second surface;   the second conductor structure comprises a third surface and a fourth surface along the vertical direction, and the third surface is close to the semiconductor layer relative to the fourth surface; and   the first surface and the third surface are coplanar.   
     
     
         5 . The semiconductor device of  claim 1 , wherein
 the bonding structure comprises a dielectric layer and bonding pad in the dielectric layer; and   the bonding pad is connected with at least one of the memory string and the peripheral circuit.   
     
     
         6 . The semiconductor device of  claim 1 , wherein
 the bonding structure comprises an array interconnection layer located between the peripheral circuit and the first side of the stacked structure;   the array interconnection layer comprises an array interconnection structure and a first bonding pad; and   the array interconnection structure is located between and connected with the first bonding pad and the memory string in the vertical direction.   
     
     
         7 . The semiconductor device of  claim 6 , wherein
 the bonding structure comprises a peripheral interconnection layer located between the array interconnection layer and the peripheral circuit;   the peripheral interconnection layer comprises a peripheral interconnection structure and a second bonding pad; and   the peripheral interconnection structure is located between and connected with the second bonding pad and the peripheral circuit in the vertical direction.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the first bonding pad and the second bonding pad are contacted and connected in the vertical direction. 
     
     
         9 . The semiconductor device of  claim 2 , further comprising a through contact penetrating through the semiconductor layer and connected with the conductor structure and the peripheral circuit, wherein the through contact is isolated from the semiconductor layer. 
     
     
         10 . The semiconductor device of  claim 2 , wherein the semiconductor layer comprises a single crystalline silicon. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the memory sting comprises a NAND string. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the NAND string comprises:
 a semiconductor channel extending vertically through the stacked structure;   a tunneling layer between the stacked structure and the semiconductor channel; and   a storage layer between the tunneling layer and the stacked structure.   
     
     
         13 . A method for forming a semiconductor device, comprising:
 forming a peripheral circuit;   forming a stacked structure comprising a first side and a second side along a vertical direction, and comprising alternating conductive layers and first insulating layers;   forming memory strings extending through the stacked structure from the second side of the stacked structure;   bonding the memory strings and the peripheral circuit;   forming a second dielectric layer on the second side of the stacked structure; and   forming conductor structures located in the second dielectric layer.   
     
     
         14 . The method of  claim 13 , further comprising prior to bonding the memory strings and the peripheral circuit, forming an array interconnection layer between the peripheral circuit and the first side of the stacked structure,
 wherein the array interconnection layer comprises an array interconnection structure and a first bonding pad, and the array interconnection structure is located between and connected with the first bonding pad and the memory strings in the vertical direction.   
     
     
         15 . The method of  claim 14 , further comprising prior to bonding the memory strings and the peripheral circuit, forming a peripheral interconnection layer located between the array interconnection layer and the peripheral circuit,
 wherein the peripheral interconnection layer comprises a peripheral interconnection structure and a second bonding pad, and the peripheral interconnection structure is located between and connected with the second bonding pad and the peripheral circuit in the vertical direction.   
     
     
         16 . The method of  claim 15 , wherein bonding the memory strings and the peripheral circuit comprises bonding the first bonding pad and the second bonding pad. 
     
     
         17 . The method of  claim 13 , wherein
 forming the peripheral circuit comprises obtaining a substrate and forming the peripheral circuit on the substrate; and   forming the stacked structure comprises forming an initial semiconductor layer and forming the stacked structure on the initial semiconductor layer.   
     
     
         18 . The method of  claim 17 , wherein
 forming the second dielectric layer on the second side of the stacked structure comprises thinning the initial semiconductor layer to a semiconductor layer, and forming the second dielectric layer on the semiconductor layer; and   the semiconductor layer is located between the second side of the stacked structure and the second dielectric layer.   
     
     
         19 . The method of  claim 18 , further comprising forming a through contact extending through the semiconductor layer and connected with the conductor structures and the peripheral circuit. 
     
     
         20 . The method of  claim 13 , wherein the bonding comprises at least one of a thermal treatment and a plasma treatment.