Method of manufacturing a FinFET by implanting a dielectric with a dopant

Abstract

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

What is claimed is: 
     
       1. A method comprising:
 forming a gate stack over a semiconductor fin; 
 forming an epitaxial source/drain region in the semiconductor fin adjacent the gate stack; 
 depositing a first dielectric layer over the gate stack and over the epitaxial source/drain region; 
 forming an opening in the first dielectric layer to expose the epitaxial source/drain region; 
 depositing a sacrificial material within the opening; 
 depositing a conductive material over the sacrificial material within the opening; 
 removing the sacrificial material to form a recess; and 
 implanting the first dielectric layer with a dopant, wherein after implanting the first dielectric layer the recess is covered by the first dielectric layer. 
 
     
     
       2. The method of  claim 1 , wherein the sacrificial material is silicon. 
     
     
       3. The method of  claim 1 , further comprising depositing a second dielectric layer on the sacrificial material within the opening. 
     
     
       4. The method of  claim 1 , further comprising depositing a third dielectric layer over the first dielectric layer before implanting the first dielectric layer. 
     
     
       5. The method of  claim 1 , wherein the dopant comprises Ge, Ar, Xe, or Si. 
     
     
       6. The method of  claim 1 , wherein the dopant is implanted in the first dielectric layer to a depth in the range of 0 nm and 20 nm. 
     
     
       7. The method of  claim 1 , wherein before implanting the first dielectric layer with the dopant, a top surface of the first dielectric layer has a first height, and after implanting the first dielectric layer with the dopant, the top surface of the first dielectric layer has a second height that is greater than the first height. 
     
     
       8. The method of  claim 1 , wherein implanting the first dielectric layer with the dopant forms doped regions near the top of the epitaxial source/drain region. 
     
     
       9. A method comprising:
 forming a fin protruding from a semiconductor substrate; 
 forming a gate structure over a channel region of the fin; 
 forming an epitaxial source/drain region in the fin adjacent the channel region; 
 forming a first inter-layer dielectric (ILD) layer over the epitaxial source/drain region; 
 forming a second ILD layer over the gate structure and over the first ILD; 
 forming a source/drain contact penetrating through the first ILD and the second ILD to physically contact the epitaxial source/drain region, wherein the source/drain contact is surrounded by a first spacer layer and a second spacer layer; 
 etching the first spacer layer to expose sidewalls of the second spacer layer; and 
 performing an implantation process on the second ILD, wherein the implantation process laterally expands a first portion of the second ILD to physically contact an exposed sidewall of the second spacer layer. 
 
     
     
       10. The method of  claim 9 , wherein the implantation process comprises implanting a dopant at an angle that is in the range of 1 degree and 60 degrees from a vertical axis. 
     
     
       11. The method of  claim 9 , wherein the implantation process comprises implanting a dopant at a dose between 10 14  atoms/cm 2  and 10 16  atoms/cm 2 . 
     
     
       12. The method of  claim 9 , wherein the second spacer layer comprises silicon nitride. 
     
     
       13. The method of  claim 9 , wherein etching the first spacer layer exposes sidewalls of the second ILD. 
     
     
       14. The method of  claim 9 , wherein after performing the implantation process, a second portion of the second ILD below the first portion of the second ILD remains unexpanded. 
     
     
       15. The method of  claim 9  further comprising forming a third spacer layer over the gate structure, wherein etching the first spacer layer exposes sidewalls of the third spacer layer. 
     
     
       16. A method comprising:
 forming an epitaxial source/drain region in a semiconductor fin; 
 forming an isolation region over the epitaxial source/drain region; 
 forming a contact on the epitaxial source/drain region, wherein an air gap separates the contact and the isolation region; and 
 sealing the air gap, comprising implanting the isolation region with a dopant. 
 
     
     
       17. The method of  claim 16 , wherein forming the contact comprises:
 etching an opening in the isolation region; 
 depositing a sacrificial layer in the opening; 
 depositing conductive material over the sacrificial layer; and 
 removing the sacrificial layer using an etching process. 
 
     
     
       18. The method of  claim 16 , wherein a top surface of the epitaxial source/drain region is exposed by the air gap. 
     
     
       19. The method of  claim 16  further comprising, before implanting the isolation region, depositing a capping layer on the isolation region. 
     
     
       20. The method of  claim 19 , wherein the capping layer extends into the air gap.