Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction

Abstract

A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.

1 . A method for making a semiconductor device comprising: 
 forming a dielectric layer on a substrate;    forming a trench within the dielectric layer, the trench having a sidewall;    exposing at least part of the sidewall to an active component to inhibit formation of a high-k dielectric layer on the surface of the sidewall; and    forming a high-k gate dielectric layer within the trench without forming a meaningful amount of a high-k dielectric layer on the surface of the sidewall.    
   
   
       2 . The method of  claim 1  wherein at least part of the sidewall is exposed to an etch chemistry.  
   
   
       3 . The method of  claim 2  wherein the etch chemistry is a dry etch chemistry.  
   
   
       4 . The method of  claim 2  wherein the etch chemistry is a wet etch chemistry.  
   
   
       5 . The method of  claim 4  wherein the wet etch chemistry comprises hydrogen.  
   
   
       6 . The method of  claim 5  wherein the wet etch chemistry comprises hydrogen fluoride.  
   
   
       7 . A method for making a semiconductor device comprising: 
 forming a dielectric layer on a substrate;    forming a first trench within the dielectric layer, the first trench having a first sidewall;    exposing at least part of the first sidewall to a first active component to inhibit formation of a first high-k dielectric layer on the surface of the first sidewall;    forming a first high-k gate dielectric layer within the first trench without forming a meaningful amount of the first high-k dielectric layer on the surface of the first sidewall;    forming a first metal layer on the first high-k gate dielectric layer;    forming a second trench within the dielectric layer, the second trench having a second sidewall;    exposing at least part of the second sidewall to a second active component to inhibit formation of a second high-k dielectric layer on the surface of the second sidewall;    forming a second high-k gate dielectric layer within the second trench without forming a meaningful amount of the second high-k dielectric layer on the surface of the second sidewall; and    forming a second metal layer on the second high-k gate dielectric layer.    
   
   
       8 . The method of  claim 7  wherein the first high-k gate dielectric layer and the second high-k gate dielectric layer each comprise a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.  
   
   
       9 . The method of  claim 7  wherein the first metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and the second metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.  
   
   
       10 . The method of  claim 7  wherein at least part of the first sidewall is exposed to an etch chemistry and at least part of the second sidewall is exposed to an etch chemistry.  
   
   
       11 . The method of  claim 10  wherein the etch chemistry is a dry etch chemistry.  
   
   
       12 . The method of  claim 10  wherein the etch chemistry is a wet etch chemistry.  
   
   
       13 . The method of  claim 12  wherein the wet etch chemistry comprises hydrogen.  
   
   
       14 . The method of  claim 13  wherein the wet etch chemistry comprises hydrogen fluoride.  
   
   
       15 . The method of  claim 7  further comprising: 
 removing a first polysilicon containing layer to form the first trench;    removing a first part of a dummy dielectric layer after exposing at least part of the first sidewall to the first active component, and before forming the first high-k gate dielectric layer within the first trench;    removing a second polysilicon containing layer to form the second trench; and    removing a second part of the dummy dielectric layer after exposing at least part of the second sidewall to the second active component, and before forming the second high-k gate dielectric layer within the second trench.    
   
   
       16 . A method for making a semiconductor device comprising: 
 forming on a substrate a dummy dielectric layer that is covered by a first polysilicon containing layer and a second polysilicon containing layer;    removing the first polysilicon containing layer to form a first trench, the first trench having a first sidewall;    exposing at least part of the first sidewall to a first active component to inhibit formation of a first high-k dielectric layer on the surface of the first sidewall;    removing a first part of the dummy dielectric layer;    forming a first high-k gate dielectric layer within the first trench without forming a meaningful amount of the first high-k dielectric layer on the surface of the first sidewall;    forming a first metal layer on the first high-k gate dielectric layer;    removing the second polysilicon containing layer to form a second trench, the second trench having a second sidewall;    exposing at least part of the second sidewall to a second active component to inhibit formation of a second high-k dielectric layer on the surface of the second sidewall;    removing a second part of the dummy dielectric layer;    forming a second high-k gate dielectric layer within the second trench without forming a meaningful amount of the second high-k dielectric layer on the surface of the second sidewall; and    forming a second metal layer on the second high-k gate dielectric layer.    
   
   
       17 . The method of  claim 16  wherein the first high-k gate dielectric layer and the second high-k gate dielectric layer each comprise a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.  
   
   
       18 . The method of  claim 16  wherein the first metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and the second metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.  
   
   
       19 . The method of  claim 16  wherein at least part of the first sidewall is exposed to a dry etch chemistry and at least part of the second sidewall is exposed to a dry etch chemistry.  
   
   
       20 . The method of  claim 16  wherein at least part of the first sidewall is exposed to a wet etch chemistry and at least part of the second sidewall is exposed to a wet etch chemistry.