Metal cap for contact resistance reduction

Abstract

A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

What is claimed is: 
     
         1 . A contact stack of a semiconductor device comprising: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer in direct contact with the metal silicide layer; and a conductor in contact with the metal cap layer. 
     
     
         2 . The contact stack of  claim 1 , wherein the source/drain region comprises: silicon, germanium, silicon-germanium, or a group III/V compound semiconductor. 
     
     
         3 . The contact stack of  claim 1 , wherein the metal silicide layer comprises: titanium silicide, cobalt silicide, ruthenium silicide, nickel silicide, molybdenum silicide, or alloys thereof. 
     
     
         4 . The contact stack of  claim 1 , wherein the metal cap layer comprises: tungsten, ruthenium, molybdenum, or alloys thereof. 
     
     
         5 . The contact stack of  claim 1 , wherein the conductor comprises a metal selected from the group consisting of: tungsten, ruthenium, and cobalt. 
     
     
         6 . The contact stack of  claim 1  excluding a metal nitride layer in direct contact with the metal silicide layer. 
     
     
         7 . A semiconductor device comprising:
 a contact stack on the substrate, the contact stack comprising:
 a source/drain region comprising: silicon, germanium, silicon-germanium, or a group III/V compound semiconductor; 
 a metal silicide layer on the source/drain region, the metal silicide layer comprising: titanium silicide, cobalt silicide, ruthenium silicide, nickel silicide, molybdenum silicide, or alloys thereof; 
 a metal cap layer directly on the metal silicide layer, the metal cap layer comprising: tungsten, ruthenium, molybdenum, or alloys thereof; and 
 a conductor on the metal cap layer; and 
   a dielectric layer adjacent to the contact stack, and   a metal gate adjacent to the dielectric layer.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the dielectric layer in direct contact with the contact stack. 
     
     
         9 . The semiconductor device of  claim 7  excluding a metal nitride layer in direct contact with the metal silicide layer. 
     
     
         10 . A method comprising:
 depositing a metal silicide layer in a feature of a substrate in a first processing chamber, the feature comprising a bottom wall and sidewalls;   moving the substrate to a second processing chamber that is integrated with the first processing chamber such that there is not an air break between the first and second processing chambers;   preparing a metal cap layer directly on the metal silicide layer; and   depositing a conductor on the metal cap layer.   
     
     
         11 . The method  claim 10 , wherein the feature comprises a source/drain region as the bottom wall, and a dielectric material as the sidewalls. 
     
     
         12 . The method  claim 10 , wherein the metal silicide layer is deposited selectively on the bottom wall. 
     
     
         13 . The method  claim 10 , wherein the conductor is deposited selectively on the metal cap layer. 
     
     
         14 . The method of  claim 10 , wherein the preparing of the metal cap layer directly on the metal silicide layer is by a physical vapor deposition (PVD) process of a metal cap material. 
     
     
         15 . The method of  claim 14 , wherein the PVD process is conducted under conditions of: a chamber temperature of 350° C. to 450° C.; a chamber pressure of 120 mT ±50 mT; a bias in a range of 0 W to 200 W; a direct current (DC) of 0 W to 500 W; and a radio frequency (RF) in a range of 1 kHz to 10 kHz. 
     
     
         16 . The method of  claim 14 , wherein the preparing of the metal cap layer comprises depositing of the metal cap material, depositing a spin-on or gap-fill material, and thereafter etching of at least a portion of the spin-on or gap-fill material and the metal cap material. 
     
     
         17 . The method of  claim 16  comprising further etching of the metal cap material. 
     
     
         18 . The method of  claim 14 , wherein the preparing of the metal cap layer comprises depositing of the metal cap material, depositing a spin-on or gap-fill material, and thereafter chemical mechanical polishing (CMP) of at least a portion of the spin-on or gap-fill material and the metal cap material. 
     
     
         19 . The method of  claim 18  comprising further etching of the metal cap material. 
     
     
         20 . The method of  claim 10 , wherein the metal silicide layer comprises: titanium silicide, cobalt silicide, ruthenium silicide, nickel silicide, molybdenum silicide, or alloys thereof; and/or the metal cap layer comprises: tungsten, ruthenium, molybdenum, or alloys thereof, and/or the conductor comprises a metal selected from the group consisting of: tungsten, ruthenium, and cobalt.