Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of nanowires than the second vertical arrangement of nanowires, the first and second vertical arrangements of nanowires having uppermost nanowires at a same level, and the first vertical arrangement of nanowires having a bottommost nanowire below a bottommost nanowire of the second arrangement of nanowires;   an oxide structure beneath the bottommost nanowire of the second arrangement of nanowires;   a first gate stack over and around the first vertical arrangement of nanowires; and   a second gate stack over and around the second vertical arrangement of nanowires and over and around the oxide structure.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the oxide structure is laterally spaced apart from the bottommost nanowire of the first vertical arrangement of nanowires. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width the same as a horizontal width of the nanowires of the second vertical arrangement of nanowires. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width less than a horizontal width of the nanowires of the second vertical arrangement of nanowires. 
     
     
         6 . The integrated circuit structure of  claim 1 , further comprising:
 first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires; and   second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires.   
     
     
         7 . The integrated circuit structure of  claim 6 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures. 
     
     
         8 . The integrated circuit structure of  claim 6 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures. 
     
     
         9 . The integrated circuit structure of  claim 6 , wherein the first gate stack has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate stack, and wherein the second gate stack has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate stack. 
     
     
         10 . The integrated circuit structure of  claim 6 , further comprising:
 a first pair of conductive contact structures coupled to the first epitaxial source or drain structures; and   a second pair of conductive contact structures coupled to the second epitaxial source or drain structures.   
     
     
         11 . The integrated circuit structure of  claim 1 , wherein the first vertical arrangement of nanowires is over a first fin, and the second vertical arrangement of nanowires is over a second fin. 
     
     
         12 . The integrated circuit structure of  claim 1 , further comprising:
 a gate endcap isolation structure between and in contact with the first gate stack and the second gate stack.   
     
     
         13 . The integrated circuit structure of  claim 1 , wherein the first and second gate stacks each comprise a high-k gate dielectric layer and a metal gate electrode. 
     
     
         14 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of nanowires than the second vertical arrangement of nanowires, the first and second vertical arrangements of nanowires having uppermost nanowires at a same level, and the first vertical arrangement of nanowires having a bottommost nanowire below a bottommost nanowire of the second arrangement of nanowires; 
 an oxide structure beneath the bottommost nanowire of the second arrangement of nanowires; 
 a first gate stack over and around the first vertical arrangement of nanowires; and 
 a second gate stack over and around the second vertical arrangement of nanowires and over and around the oxide structure. 
   
     
     
         15 . The computing device of  claim 14 , further comprising:
 a memory coupled to the board.   
     
     
         16 . The computing device of  claim 14 , further comprising:
 a communication chip coupled to the board.   
     
     
         17 . The computing device of  claim 14 , further comprising:
 a battery coupled to the board.   
     
     
         18 . The computing device of  claim 14 , further comprising:
 a camera coupled to the board.   
     
     
         19 . The computing device of  claim 14 , wherein the component is a packaged integrated circuit die. 
     
     
         20 . The computing device of  claim 14 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.