Field effect transistor with isolated source/drains and methods

Abstract

A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

What is claimed is: 
     
         1 . A device, comprising:
 a substrate having a semiconductor fin;   a stack of semiconductor channels on the substrate and positioned over the fin;   a gate structure wrapping around the semiconductor channels;   a source/drain abutting the semiconductor channels;   an inner spacer positioned between the stack of semiconductor channels and the fin;   an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and   an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.   
     
     
         2 . The device of  claim 1 , wherein the isolation structure has thickness that is in a range of about 1 nanometer to about 3 nanometers. 
     
     
         3 . The device of  claim 1 , wherein the isolation structure is in direct contact with the source/drain. 
     
     
         4 . The device of  claim 1 , further comprising a bottom isolation layer, the isolation structure being separated from the source/drain by the bottom isolation layer. 
     
     
         5 . The device of  claim 1 , further comprising an implantation region between the undoped semiconductor layer and the source/drain, a first type of dopant species in the implantation region being opposite a second type of the source/drain. 
     
     
         6 . The device of  claim 5 , further comprising a second semiconductor layer between the implantation region and the source/drain. 
     
     
         7 . The device of  claim 6 , further comprising a bottom isolation layer between the source/drain and the second semiconductor layer. 
     
     
         8 . The device of  claim 1 , further comprising:
 a second stack of semiconductor channels offset from the stack of semiconductor channels;   a second source/drain abutting the second stack of semiconductor channels; and   a second implantation region beneath the second source/drain, a third type of dopant species in the second implantation region being opposite the first type of dopant species in the implantation region.   
     
     
         9 . The device of  claim 8 , further comprising a third semiconductor layer between the second implantation region and the second source/drain. 
     
     
         10 . The device of  claim 9 , wherein the second source/drain is in direct contact with the third semiconductor layer and the source/drain is isolated from the second semiconductor layer by a bottom isolation layer. 
     
     
         11 . A method, comprising:
 forming a stack of semiconductor nanostructure layers over a substrate;   forming a stack of semiconductor nanostructures by forming a source/drain opening through the stack of semiconductor nanostructure layers;   forming a dielectric layer on surfaces exposed by the source/drain opening;   forming a first semiconductor layer on the dielectric layer in the source/drain opening;   forming an isolation structure by removing portions of the dielectric layer exposed by the first semiconductor layer; and   forming a source/drain on the first semiconductor layer and abutting the stack of semiconductor nanostructures.   
     
     
         12 . The method of  claim 11 , further comprising forming an exposed portion of the substrate by removing a horizontal portion of the dielectric layer, wherein the forming a semiconductor layer includes growing the semiconductor layer on the exposed portion. 
     
     
         13 . The method of  claim 11 , wherein the forming a source/drain includes growing the source/drain directly on the first semiconductor layer. 
     
     
         14 . The method of  claim 11 , further comprising forming a bottom insulator on the first semiconductor layer, wherein the forming a source/drain includes growing the source/drain from the stack of semiconductor nanostructures without substantially growing the source/drain from the first semiconductor layer. 
     
     
         15 . The method of  claim 11 , further comprising:
 forming a second stack of semiconductor nanostructures offset from the first stack of semiconductor nanostructures by forming a second source/drain opening in the stack of nanostructure layers; and   during the forming a first semiconductor layer, forming a second semiconductor layer that has side surfaces in direct contact with a fin over which the second stack of semiconductor nanostructures is positioned.   
     
     
         16 . A method, comprising:
 forming a stack of nanostructures over a substrate by forming a source/drain opening;   forming a first semiconductor layer in the source/drain opening;   forming an isolating layer in the source/drain opening on the first semiconductor layer;   forming an isolation layer by thinning the isolating layer, the forming an isolation layer exposing an upper surface of the first semiconductor layer;   forming an implantation region including first dopants of a first type by directing the first dopants onto the upper surface of the first semiconductor layer;   forming a second semiconductor layer on the implantation region;   forming an isolation structure by removing portions of the isolation layer exposed by the second semiconductor layer; and   forming a source/drain on the second semiconductor layer, the source/drain being of a second type different than the first type.   
     
     
         17 . The method of  claim 16 , wherein the forming a second semiconductor layer includes forming the second semiconductor layer to a level that is above at least one nanostructure of the stack of nanostructures. 
     
     
         18 . The method of  claim 16 , wherein the forming a source/drain includes growing the source/drain directly from the second semiconductor layer. 
     
     
         19 . The method of  claim 16 , further comprising:
 forming a second stack of nanostructures by forming a second source/drain opening;   forming a second implantation region in the second source/drain opening, the second implantation region including the first dopants of the first type;   forming a third semiconductor layer on the second implantation region;   forming a bottom insulator on the third semiconductor layer; and   forming a second source/drain on the bottom insulator, the second source/drain being of the first type.   
     
     
         20 . The method of  claim 16 , further comprising:
 forming a second stack of nanostructures by forming a second source/drain opening;   forming a second implantation region in the second source/drain opening, the second implantation region including second dopants of the second type;   forming a third semiconductor layer on the second implantation region; and   forming a second source/drain directly from the third semiconductor layer, the second source/drain being of the first type.