Drain coupled non-linear polar material based capacitors for memory and logic

Abstract

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

What is claimed is: 
     
       1. A system comprising:
 a first region comprising:
 a transistor in a first level, the transistor comprising:
 a source; 
 a drain; 
 a gate between the source and the drain; 
 a drain contact coupled with the drain; and 
 a gate contact coupled with the gate; and 
 
 a memory coupled to the transistor, wherein the memory comprises: bit-cells, wherein one of the bit-cells comprises:
 a first conductive interconnect within a first dielectric in a second level, wherein the first conductive interconnect is electrically coupled with the drain contact, and wherein the first conductive interconnect comprises a first lateral thickness; and 
 a third level above the second level, the third level comprising:
 an electrode structure on the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer and a first conductive fill material, wherein the electrode structure comprises a second lateral thickness; 
 an etch stop layer laterally surrounding the electrode structure; 
 a plurality of memory devices above the electrode structure, wherein individual ones of the plurality of memory devices comprises a perovskite material; 
 a plate electrode coupled between the plurality of memory devices and the electrode structure, wherein the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices; 
 an insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the plurality of memory devices; and 
 a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices, and wherein the individual ones of the plurality of via electrodes comprise: 
  a second conductive hydrogen barrier layer comprising a lateral portion and substantially vertical portions connected to two ends of the lateral portion; and 
  a second conductive material on the lateral portion and between the substantially vertical portions; and 
 
 
 
 a second region adjacent to the first region, the second region comprising:
 a second conductive interconnect within the second level, wherein the third level further comprises:
 a metal structure; and 
 a via structure coupled between the second conductive interconnect and the metal structure, wherein at least a sidewall of the via structure is adjacent to the etch stop layer. 
 
 
 
     
     
       2. The system of  claim 1 , wherein the plate electrode extends beyond a first perimeter of the individual ones of the plurality of memory devices, and wherein the plate electrode extends beyond a second perimeter of the electrode structure. 
     
     
       3. The system of  claim 1 , wherein the plate electrode comprises a first thickness under the individual ones of the plurality of memory devices and a second thickness away from the individual ones of the plurality of memory devices. 
     
     
       4. The system of  claim 3 , wherein the insulative hydrogen barrier layer further comprises:
 a first portion that is substantially aligned with a third perimeter of the plate electrode; and 
 a second portion between the individual ones of the plurality of memory devices and a third portion on the individual ones of the plurality of memory devices. 
 
     
     
       5. The system of  claim 1 , wherein the individual ones of the plurality of memory devices are spaced apart by a distance between at least 10 nm. 
     
     
       6. The system of  claim 1 , wherein the electrode structure is laterally between a pair of memory devices in the plurality of memory devices. 
     
     
       7. The system of  claim 1 , wherein the electrode structure is directly between a memory device in the plurality of memory devices and the first conductive interconnect. 
     
     
       8. The system of  claim 1 , wherein the plate electrode comprises:
 a third portion that extends along a first direction on a first plane; 
 a fourth portion that extends parallel to the first direction, the fourth portion on a second plane, the second plane behind the first plane; and 
 a fifth portion that extends orthogonally from the third portion to the fourth portion. 
 
     
     
       9. The system of  claim 8 , wherein the third portion is connected to a first midpoint of the third portion to a second midpoint of the fourth portion, and wherein the plate electrode comprises:
 a first pair of memory devices in the plurality of memory devices on the third portion; 
 a second pair of memory devices in the plurality of memory devices on the fourth portion; and 
 at least one memory device in the plurality of memory devices on the fifth portion. 
 
     
     
       10. The system of  claim 1 , wherein the individual ones of the plurality of memory devices comprises a circular, an elliptical or a rectangular plan view profile. 
     
     
       11. The system of  claim 1 , wherein the second lateral thickness is less than the first lateral thickness. 
     
     
       12. The system of  claim 1 , wherein the perovskite material comprises:
 bismuth ferrite (BFO) or BFO with a first doping material, wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table; 
 lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb; 
 a relaxor ferroelectric material which includes one of; lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST); 
 a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ; a hexagonal ferroelectric which includes one of: YMnO 3 , or LuFeO 3 ;
 hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); 
 
 hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides; 
 hafnium oxides as Hf (1-x) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where x and y are first and second fractions, respectively; 
 Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively; 
 y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; 
 niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100; or 
 a paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3  (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectric, and 
 wherein the individual ones of the plurality of memory devices comprise a conductive layer comprising one of La—Sr—CoO 3 , SrRuO 3 , La—Sr—MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , or LaNiO 3 . 
 
     
     
       13. The system of  claim 1 , wherein the first conductive hydrogen barrier layer is between the first conductive interconnect and the first conductive fill material, and wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N 2 , TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti 2 O, WO 3 , SnO 2 , ITO, IGZO, ZO, or METGLAS series of alloys. 
     
     
       14. A system comprising:
 a first region comprising:
 a transistor in a first level, the transistor comprising:
 a source; 
 a drain; 
 a gate between the source and the drain; 
 a drain contact coupled with the drain; and 
 a gate contact coupled with the gate; and 
 
 a memory coupled to the transistor, wherein the memory comprises: bit-cells, wherein one of the bit-cells comprises:
 a first conductive interconnect within a first dielectric in a second level, wherein the first conductive interconnect is electrically coupled with the drain contact, and wherein the first conductive interconnect comprises a first lateral thickness; and 
 a third level above the second level, the third level comprising:
 an electrode structure on the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer and a first conductive fill material, wherein the electrode structure comprises a second lateral thickness; 
 an etch stop layer laterally surrounding the electrode structure; 
 a plate electrode on the electrode structure, the plate electrode extending beyond a perimeter of the electrode structure on the etch stop layer; 
 a second dielectric on the plate electrode and on the etch stop layer; 
 a plurality of trenches within the second dielectric; 
 a plurality of trench capacitors, wherein individual ones of the plurality of trench capacitors are in individual ones of the plurality of trenches, and wherein the individual ones of the plurality of trench capacitors comprise: 
  a dielectric spacer along a sidewall of the individual ones of the plurality of trenches; 
  a first electrode on a base and on the dielectric spacer along the sidewall of the individual ones of the plurality of trenches, wherein the first electrode is in contact with the plate electrode; 
  a dielectric layer comprising a ferroelectric material or a paraelectric material substantially conformal to the first electrode; and 
  a second electrode in contact with the dielectric layer; and 
 a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on the second electrode of the individual ones of the plurality of trench capacitors, wherein the individual ones of the plurality of via electrodes comprise: 
  a second conductive hydrogen barrier layer comprising a lateral portion in contact with the second electrode and substantially vertical portions connected to the lateral portion; and 
  a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and 
 
 
 
 a second region adjacent to the first region, the second region comprising:
 a second conductive interconnect within the second level, wherein the third level further comprises:
 a metal structure; and 
 a via structure coupled between the second conductive interconnect and the metal structure, wherein at least a first portion of the via structure is adjacent to the etch stop layer. 
 
 
 
     
     
       15. The system of  claim 14 , further comprising a third dielectric on the second dielectric and portions of the individual ones of the plurality of trench capacitors, wherein the third dielectric comprises a material having 90% of theoretical material density such as but not limited to Al x O y , HfO x , AlSiO x , ZrO x , TiO x , AlSiO x , HfSiO x , TaSiO x , AlN, ZrN, HfN, or SiN. 
     
     
       16. The system of  claim 14 , wherein the individual ones of the plurality of trench capacitors are spaced apart by a distance between at least 10 nm. 
     
     
       17. The system of  claim 14 , wherein the electrode structure is laterally between a pair of trench capacitors in the plurality of trench capacitors. 
     
     
       18. The system of  claim 14 , wherein the first region further comprises a third conductive interconnect on a same level as the first conductive interconnect, and wherein the third conductive interconnect is at least partially below the plate electrode but not coupled with the plate electrode. 
     
     
       19. A system comprising:
 a transistor in a first level, the transistor comprising:
 a source; 
 a drain; 
 a gate between the source and the drain; 
 a drain contact coupled with the drain; and 
 a gate contact coupled with the gate; and 
 
 a memory coupled to the transistor, wherein the memory comprises: bit-cells, wherein one of the bit-cells comprises:
 a plurality of conductive interconnects laterally spaced apart by a distance, the plurality of conductive interconnects within a first dielectric in a second level, wherein an individual one of the plurality of conductive interconnects is electrically coupled with the drain contact, and wherein individual ones of the plurality of conductive interconnects have a first lateral thickness; and 
 a third level above the second level, the third level comprising: 
 an electrode structure on the individual one of the plurality of conductive interconnects that is electrically coupled with the drain contact, wherein the electrode structure comprises a first conductive hydrogen barrier layer and a first conductive fill material, wherein the electrode structure comprises a second lateral thickness, and wherein the second lateral thickness is less than a combined sum of the first lateral thickness and two times the distance; 
 a plurality of memory devices above the electrode structure, wherein individual ones of the plurality of memory devices comprise a perovskite material and a first sidewall; 
 a plate electrode comprising an uppermost surface and second sidewalls, the plate electrode coupled between the plurality of memory devices and the electrode structure, wherein the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices; 
 an encapsulation layer on the first sidewall and on a portion of an uppermost surface of the individual ones of the plurality of memory devices, and on an uppermost surface of the plate electrode, wherein the encapsulation layer is aligned with the second sidewalls and wherein the encapsulation layer comprises an insulator material; 
 a dielectric spacer on the second sidewalls, wherein the dielectric spacer comprises the insulator material; and 
 a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices, and wherein the individual ones of the plurality of via electrodes comprise:
 a second conductive hydrogen barrier layer comprising a lateral portion and substantially vertical portions connected to two ends of the lateral portion; and 
 a second conductive material on the lateral portion and between the substantially vertical portions. 
 
 
 
     
     
       20. The system of  claim 19 , further comprising a signal electrode on the plate electrode, wherein the signal electrode is between a pair of memory devices in the individual ones of the plurality of memory devices, and wherein the individual ones of the plurality of memory devices comprise a planar capacitor or a trench capacitor.