Self-ionized and inductively-coupled plasma for sputtering and resputtering

Abstract

A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

1 - 82 . (canceled)  
   
   
       83 . A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising: 
 (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;    (b) etching through at least part of the first portion of the diffusion barrier at the bottoms of a plurality of vias to expose at least part of an underlying metal layer while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the wafer substrate;    (c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and    (d) depositing the metal conductive layer over the surface of the wafer substrate.    
   
   
       84 . The method of  claim 83 , wherein at least two successive operations in (a) through (c) are performed in the same processing chamber.  
   
   
       85 . The method of  claim 84 , wherein the processing chamber is a plasma physical vapor deposition (PVD) chamber.  
   
   
       86 . The method of  claim 84 , wherein the processing chamber comprises a hollow cathode magnetron.  
   
   
       87 . The method of  claim 83 , further comprising a degas operation prior to (a).  
   
   
       88 . The method of  claim 83 , wherein (b) comprises depositing the second portion of diffusion barrier elsewhere on the wafer at least as on sidewalls of the plurality of vias.  
   
   
       89 . The method of  claim 88 , wherein (b) further comprises depositing the second portion of diffusion barrier elsewhere on the wafer including on field regions of the wafer substrate.  
   
   
       90 . The method of  claim 83 , wherein (c) comprises depositing the third portion of diffusion barrier on field regions of the wafer substrate.  
   
   
       91 . The method of  claim 83 , wherein (a) comprises sputtering a metal from a target having an applied DC power of greater than 10 kilowatts, without significantly biasing the wafer substrate.  
   
   
       92 . The method of  claim 83 , wherein (a) comprises using physical vapor deposition (PVD).  
   
   
       93 . The method of  claim 83 , wherein at least one portion of the diffusion barrier comprises a material selected from the group consisting of tantalum, nitrogen-doped tantalum, tantalum nitride, titanium nitride, and tungsten nitride.  
   
   
       94 . The method of  claim 83 , wherein (b) comprises sputtering a metal from a target having an applied DC power of between about 1 and 40 kilo Watts, while applying a bias to the wafer substrate.  
   
   
       95 . The method of  claim 94 , wherein the bias comprises RF power of between about 10 and 5000 Watts.  
   
   
       96 . The method of  claim 94 , wherein (b) further comprises passing argon gas through the process chamber.  
   
   
       97 . The method of  claim 83 , wherein (b) is performed under conditions having an etch-to-deposition ratio of greater than 1 at the bottoms of the vias.  
   
   
       98 . The method of  claim 83 , wherein (c) comprises sputtering a metal from a target having an applied DC power of greater than 10 kilo Watts, without significantly biasing the wafer substrate.  
   
   
       99 . The method of  claim 83 , wherein (c) comprises a process selected from the group consisting of physical vapor deposition (PVD).  
   
   
       100 . The method of  claim 83 , further comprising, after (c) but prior to (d), etching through some of the third portion of the diffusion barrier at the bottoms of a plurality of vias, without etching to expose an underlying metal structure.  
   
   
       101 . The method of  claim 83 , wherein (d) comprises depositing copper containing metal over the surface of the wafer substrate.  
   
   
       102 . The method of  claim 101 , wherein the metal is a copper seed layer.  
   
   
       103 . The method of  claim 83 , wherein at least (a) and (b) are performed in the same processing chamber.  
   
   
       104 . The method of  claim 83 , wherein at least (b) and (c) are performed in the same processing chamber.  
   
   
       105 . The method of  claim 83 , wherein at least (a) through (c) are all performed in the same processing chamber.  
   
   
       106 . A method for depositing a diffusion barrier and a metal conductive layer on a partially fabricated integrated circuit containing a plurality of unlanded vias, the method comprising: 
 (a) depositing a first portion of the diffusion barrier on the surface of the partially fabricated integrated circuit;    (b) etching through at least part of the first portion of the diffusion barrier at the bottoms of a plurality of unlanded and landed vias to expose at least part of an underlying metal layer while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the surface of the partially fabricated integrated circuit;    (c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and    (d) depositing the metal conductive layer over the surface of the wafer substrate.    
   
   
       107 . The method of  claim 106 , further comprising a degas operation prior to (a).  
   
   
       108 . The method of  claim 106 , wherein at least two successive operations of (a), (b), and (c) are performed in the same processing chamber.  
   
   
       109 . The method of  claim 108 , wherein the processing chamber is a plasma physical vapor deposition (PVD) chamber.  
   
   
       110 . The method of  claim 108 , wherein the processing chamber comprises a hollow cathode magnetron.  
   
   
       111 . The method of  claim 106 , wherein (a) and/or (c) comprise a processes selected from the group consisting of physical vapor deposition (PVD).  
   
   
       112 . The method of  claim 106 , wherein at least one portion of the diffusion barrier comprises a material selected from the group consisting of tantalum, nitrogen-doped tantalum, tantalum nitride, titanium nitride, and tungsten nitride.  
   
   
       113 . The method of  claim 106 , wherein (b) comprises sputtering a metal from a target having an applied DC power of between about 1 and 40 kilo Watts, while applying a bias to the wafer substrate.  
   
   
       114 . The method of  claim 106 , wherein (d) comprises depositing copper-containing metal over the surface partially fabricated integrated circuit.  
   
   
       115 . The method of  claim 114 , wherein the metal is a copper seed layer.  
   
   
       116 . The method of  claim 106 , wherein at least (a) and (b) are performed in the same processing chamber.  
   
   
       117 . The method of  claim 106 , wherein at least (b) and (c) are performed in the same processing chamber.  
   
   
       118 . The method of  claim 106 , wherein at least (a) through (c) are all performed in the same processing chamber.