US2025273582A1PendingUtilityA1

Interconnections to package substrates for interconnect bridges

Assignee: INTEL CORPPriority: Feb 26, 2024Filed: Feb 26, 2024Published: Aug 28, 2025
Est. expiryFeb 26, 2044(~17.6 yrs left)· nominal 20-yr term from priority
H10W 70/611H10W 90/734H10W 72/248H10W 90/724H10W 70/635H10W 74/15H10W 70/685H10W 74/114H10W 70/65H10W 70/60H01L 2224/73204H01L 2224/32225H01L 2224/16227H01L 2224/14177H01L 24/73H01L 24/32H01L 24/16H01L 24/14H01L 23/5384H01L 23/5383H01L 23/5386
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Claims

Abstract

Semiconductor package substrates and assemblies comprising semiconductor package substrates are provided. The semiconductor package substrates can include interconnect bridges having through-bridge vias. The semiconductor package substrates can also include collapsible cavities in dielectric layers. The interconnect bridges can include protruding conductive pads that form electrical connections with the semiconductor package substrate. Assemblies include semiconductor package substrates and semiconductor devices.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 a substrate wherein the substrate comprises layers of dielectric material, wherein the substrate comprises conductive traces and vias in the layers of dielectric material, and wherein the substrate comprises one or more dielectric layers that comprise one or more gas-filled cavities; and   an interconnect bridge on the substrate wherein the interconnect bridge comprises conductive traces and conductive through-bridge vias, and wherein the interconnect bridge is electrically connected to the substrate.   
     
     
         2 . The apparatus of  claim 1  wherein the one or more gas-filled cavities comprise gas-filled glass beads, gas-filled glass fibers, or gas bubbles. 
     
     
         3 . The apparatus of  claim 1  wherein there is no underfill material between the substrate and the interconnect bridge in an interconnect region between the substrate and the interconnect bridge. 
     
     
         4 . The apparatus of  claim 1  wherein a gas-filled cavity of the one or more gas-filled cavities comprises a cavity that partially surrounds a trace in the substrate. 
     
     
         5 . The apparatus of  claim 1  wherein a gas-filled cavity of the one or more gas-filled cavities has dimensions between 3 μm and 50 μm. 
     
     
         6 . The apparatus of  claim 1  wherein the substrate also comprises a core and the core is comprised of a solid amorphous glass material. 
     
     
         7 . An apparatus comprising:
 a substrate wherein the substrate comprises layers of dielectric material, wherein the substrate comprises conductive traces and vias in the layers of dielectric material, wherein the substrate comprises first conductive pads, and wherein a layer of the layers of dielectric material comprises cavities; and   an interconnect bridge in the substrate wherein the interconnect bridge comprises conductive traces, conductive vias, and conductive through-bridge vias, wherein the interconnect bridge comprises second conductive pads that protrude from a surface of the interconnect bridge, wherein a second conductive pad protrudes into a cavity of the layer dielectric material that comprises cavities, and wherein a second conductive pad is electrically connected to a first conductive pad.   
     
     
         8 . The apparatus of  claim 7  wherein the layer of dielectric material that comprises cavities is comprised of a polyimide or a build-up film. 
     
     
         9 . The apparatus of  claim 7  wherein the layer of dielectric material that comprises cavities is comprised of a photo-imageable dielectric material. 
     
     
         10 . The apparatus of  claim 7  wherein there is no underfill material between the substrate and the interconnect bridge in an interconnect region between the substrate and the interconnect bridge. 
     
     
         11 . The apparatus of  claim 7  wherein the first conductive pads are comprised of copper. 
     
     
         12 . The apparatus of  claim 7  wherein the first conductive pads comprise one or more layers of material that are comprised of tin, gold, palladium, platinum, nickel, or a combination thereof. 
     
     
         13 . The apparatus of  claim 7  wherein the second conductive pad is electrically connected to the first conductive pad through a solder region. 
     
     
         14 . The apparatus of  claim 7  wherein the interconnect bridge is embedded in the substrate. 
     
     
         15 . The apparatus of  claim 7  wherein the substrate also comprises a core and the core is comprised of a solid amorphous glass material. 
     
     
         16 . An assembly comprising:
 a processor; and   a package substrate, wherein the package substrate comprises:
 a substrate wherein the substrate comprises layers of dielectric material, wherein conductive traces and vias are in the layers of dielectric material, wherein the substrate comprises first conductive pads, and wherein the substrate comprises a layer of dielectric material that comprises cavities; and 
 an interconnect bridge in the substrate wherein the interconnect bridge comprises conductive traces, conductive vias, and conductive through-bridge vias, wherein the interconnect bridge comprises second conductive pads that protrude from a surface of the interconnect bridge, wherein a second conductive pad protrudes into a cavity of the layer dielectric material that comprises cavities, and wherein a second conductive pads is electrically connected to a first conductive pad, 
   and wherein the processor is electrically coupled to the interconnect bridge.   
     
     
         17 . The assembly of  claim 16  wherein the layer of dielectric material that comprises cavities is comprised of a build-up film. 
     
     
         18 . The assembly of  claim 16  wherein the layer of dielectric material that comprises cavities is comprised of a photo-imageable dielectric material. 
     
     
         19 . The assembly of  claim 16  wherein the first conductive pads comprise one or more layers of material that are comprised of tin, gold, palladium, platinum, nickel, or a combination thereof. 
     
     
         20 . The assembly of  claim 16  wherein the conductive through-bridge vias are capable of supplying power from a circuit board to the processor.

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